ISD-300A1 Cypress Semiconductor Corp, ISD-300A1 Datasheet
ISD-300A1
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ISD-300A1 Summary of contents
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... ISD-300A1 High Speed USB to ATA ASIC Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 ISD-300A1 Oct 19, 2001 ...
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... DOCUMENT REVISION HISTORY ........................................................................................................ 1 PIN INFORMATION .................................................................................................................................. 2 OVERVIEW ................................................................................................................................................. 6 INTRODUCTION ........................................................................................................................................ 7 ISD-300A1 CONFIGURATION ................................................................................................................. 7 ISD-300A1 C ONFIGURATION AND Internal ROM Contents .......................................................................................................................... Memory Device Interface................................................................................................................. 8 Vendor-Specific Identify Data (FBh) ..................................................................................................... 9 ISD-300A1 C ONFIGURATION ISD-300A1 Configuration Data.............................................................................................................. 9 USB INTERFACE...................................................................................................................................... 14 D ............................................................................................................................................ 14 ESCRIPTORS Supported Descriptors .......................................................................................................................... 14 Descriptor Data Format ........................................................................................................................ ESCRIPTOR EQUIREMENTS String Descriptor Indexes ..................................................................................................................... 21 P ......................................................................................................................................................... 21 IPES Default Control Pipe ...
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... APPENDIX A – EXAMPLE EEPROM OR FBH IDENTIFY DATA CONTENTS............................ 51 .................................................................................................................. 40 – USB INS EMOTE AKEUP AND VENT IO ......................................................................................................... 41 I (FB ) ATA C PECIFIC DENTIFY H OMMAND ............................................................................................................. 41 D ............................................................................................ 42 ISABLED NTERFACE ULL UP ESISTOR OURCE NTERFACE ULL DOWN ESISTOR INK ............................................................................................................... 43 ODES .................................................................................................................. 45 ODE .......................................................................................................... 45 C ............................................................................................ 46 ONSIDERATIONS - T ........................................................................................ 47 YPICAL T ................................................................................................ 48 IMING .................................................................................................................. 49 C ........................................................................................ 49 HARACTERISTICS ii ISD-300A1 N .............................. 41 OTIFICATION (I_MODE).................................... 41 .......................................................... 42 ......................................................... 42 ...
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... October 19, 2001 Table 1 –Document Revision History ............................................................................................................ 1 Table 2 – Pin Descriptions ............................................................................................................................. 5 Table 3 – ISD-300A1 Configuration and Descriptor Sources ........................................................................ 8 Table 4 – ISD-300A1 Configuration Bytes .................................................................................................. 14 Table 5 – Device Descriptor......................................................................................................................... 16 Table 6 – Device Qualifier Descriptor.......................................................................................................... 16 Table 7 – Standard Configuration Descriptor(s)........................................................................................... 17 Table 8 – Other Speed Configuration Descriptor(s) ..................................................................................... 18 Table 9 – ...
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... Figure 2 – ATA Reset Protocol .................................................................................................................... 29 Figure 3– ATA Command Block Flow Diagram ......................................................................................... 34 Figure 4 – SYS_IRQ – USB Interrupt Pipe.................................................................................................. 42 Figure 5 – External Components connection................................................................................................ 45 2 Figure 6 – Memory Device Interface Timing......................................................................................... 48 Figure 7 – SYS_IRQ Interface Timing......................................................................................................... 49 Figure 8 – Package Outline Diagram............................................................................................................ 50 Table of Figures iv ISD-300A1 ...
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... April 18, 2001 0.9 June 19, 2001 1.0 July 10, 2001 1.01 Aug 1, 2001 1.02 October 19, 2001 Table 1 –Document Revision History ISD-300A1 ASIC Datasheet Cypress Semiconductor 0.8 January 16, 2001 Comments Initial revision Grammar edits. 2 Identified I C limitations Rolled version to release draft Minor corrections, rolled to final release draft. ...
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... DD9 86 DD6 87 DD8 88 DD7 89 NATA_RESET 90 VDD 91 NPWR500 92 93 VSS NLED1 94 95 NLED0 SDA 96 SCL 97 SYS_IRQ 98 DISK_READY 99 VSS 100 Figure 1 – Pin Layout ISD-300A ISD-300A1 VSS GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 VDD GPIO3 VSS GPIO2 GPIO1 GPIO0 NCART_DET NEJECT NRESET I_MODE ...
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... I LVTTL, 5V Active low. Media present indication. If remote tolerant, wakeup is enabled by the USB host, a state hysteresis change on this pin will cause the ISD-300A1 to perform a USB remote wakeup event. Filtered internally by ISD-300A1. Set NCART_DET = 1 if the functionality is not utilized. 3 ISD-300A1 ...
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... Active low. Media eject requested. If remote tolerant, wakeup is enabled by the USB host, a state hysteresis change on this pin will cause the ISD-300A1 to perform a USB remote wakeup event. Filtered internally by ISD-300A1. Set NEJECT = 1 if the functionality is not utilized LVTTL clock. Open drain during normal operation. ...
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... PLL voltage reference. Current source for 9.1K ohm resistor (1%) connected to AVSS. I ASIC test Fabrication only. Connect to VSS. I ASIC test Fabrication only. Connect to VSS. Analog 3.3V supply (PLL) Analog 3.3V ground (PLL) Analog 3.3V supply Analog ground 3.3V digital supply Digital ground 5 ISD-300A1 ...
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... Command Blocks Utilizing the MSC Command Block Wrapper) • Provisions To Share ATA Bus With Other Hosts • Manufacturing Interconnect Test Support Provided With Vendor Specific USB Commands ♦ Read / Write Access To Relevant ASIC Pins • Utilizes Inexpensive 30Mhz Crystal For Clock Source 6 ISD-300A1 ...
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... CBW command queuing, which with vendor specific drivers allows data transfer rates the USB theoretical maximum. The USB port of the ISD-300A1 is connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the ISD-300A1 and receives status and data from the ISD-300A1 using standard USB protocol ...
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... Once the signature check passes detected initially always assumed present until the next reset cycle (NRESET present, a lack of an ACK response when required causes the ISD-300A1 to stall that USB request. The ISD-300A1 will attempt the access again with the next USB request. ...
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... For vendor specific identify data (FBh deemed valid, it must pass the signature check (first two data bytes must equal 0x4D54). In the event of a failed signature check, the ISD-300A1 will respond to all USB GET_DESCRIPTOR or GET_CONFIGURATION commands by returning defaults contained in internal ROM. ...
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... ATAPI device 1 ATA device or possible device initialization failure. Bit(2) Force USB full speed only operation. Setting this bit prevents the ISD-300A1 from negotiating HS operation during USB reset events 0 Normal operation – allow HS negotiation during USB reset 1 USB FS only – do not allow HS negotiation during USB reset Bit(1) Vendor Specific / MSC SOFT_RESET control ...
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... Device must be set’1’ in conjunction with Skip ATA/ATAPI Device Initialization and ATA Translation Enable. Software must issue an INQUIRY command followed with a MSC reset to allow the ISD-300A1 to parse drive information and optimize system performance and operation. Force ATA Device should be set ‘0’ for devices that support ISD-300A1 device initialization algorithms ...
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... Use timing information acquired from the Drive 1 Override device timing information with configuration values Bit (2) Enable for the DRV_PWR_VALID pin. Drive Power Valid should only be enabled in cable applications where the ISD-300A1 is VBUS powered. 0 pin disabled (most systems) 1 pin enabled Bit(1) PIO data read 3-state control. Enabling this will 3-state (hi-Z) the ATA data bus during PIO read operations while addressing the data register. In most applications this bit is set to ‘ ...
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... Enable ATAPI device UDMA support Bits(2:0) ROM UDMA Mode indicates the highest UDMA mode supported by the product. The ISD-300A1 will utilize the lesser of ROM UDMA Mode or the highest mode supported by the device. Note: UDMA read operation mode timing is controlled by the device. ...
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... General Purpose IO 0xF General Purpose IO 3- state control Table 4 – ISD-300A1 Configuration Bytes USB Interface The ISD-300A1 is electrically and logically compliant with the Universal Serial Bus Specification Revision 2.0. Descriptors Supported Descriptors • Device • USB Device Qualifier The ISD-300A1 requires only one Device Qualifier descriptor ...
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... VBUS_POWERED signal is active. Other Speed Configuration non-bus-powered. This configuration descriptor is reported if the VBUS_POWERED input is inactive. • Interface The ISD-300A1 supports two interface descriptors, both FS (full speed) and HS (high speed), each with four possible endpoints. • Endpoint The ISD-300A1 supports the following endpoints: Default Control endpoint ...
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... Device Qualifier Descriptor The device qualifier descriptor describes information about a high-speed capable device that would change if the device were operating at the other speed. For the ISD-300A1, none of the descriptor information requires modification, thus only one Device Qualifier Descriptor is required. The ISD-300A1 returns the same descriptor while operating in either full speed or high speed mode ...
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... This descriptor describes a configuration of a high-speed capable device if it were operating at its other possible speed. Although two descriptors are not required to distinguish differences between full speed and high speed operation, the ISD-300A1 supports two other speed configuration descriptors to enumerate differences between VBUS powered and self powered operation. The first configuration is returned when the VBUS_POWERED signal is active, the second configuration when the VBUS_POWERED signal is inactive ...
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... Interface Descriptor This descriptor specifies the interface within a configuration. There are two interface descriptors in the ISD-300A1, one for high speed, and one for full speed. Each interface contains four endpoint descriptors: Default Control (no descriptor), Bulk out, Bulk in, and Interrupt. Interface and endpoint descriptors cannot be directly accessed using the Get_Descriptor USB command ...
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... Manufacturer string begins at address 0x92, but is specified in the iManufacturer field as 0x49). String index 0 must contain the LANGID of exactly one language, as the ISD-300A1 supports only a single language. Microsoft defines the LANGID codes for Windows, as described in Developing International Software for Windows 95 and Windows NT, Nadine Kano, Microsoft Press, Redmond, Washington ...
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... ASCII character. (“NUL”) ASCII character. (“NUL”) ASCII character. (“NUL”) ASCII character. (“NUL”) ASCII character. (“NUL”) 20 ISD-300A1 On-board Defaults 0x22 0x03 0x49 (“I”) 0x00 0x6E (“n”) 0x00 0x2D (“-“) 0x00 0x53 (“S”) 0x00 0x79 (“ ...
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... I Pipes The ISD-300A1 provides four USB pipes: Default Control, Bulk Out, Bulk In, and Interrupt. Default Control Pipe The default pipe is used to transport standard, class and vendor-specific USB requests to the ISD-300A1. Bulk Out Pipe Description ASCII character. ...
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... GET_MAX_LUN The ISD-300A1 returns one byte of data that contains the maximum LUNs supported by the device. This information is derived from the Last LUN Identifier configuration setting, bits (2:0) of configuration data located at address offset 0x8. For example, if the device supports four LUNs then the LUNs would be ...
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... Last LUN Identifier configuration data bit field should be set to 0x3 LUN is associated with the device, the Last LUN Identifier shall be set to 0x0. Vendor-Specific Requests Vendor specific requests supported by the ISD-300A1 are listed in Table 12. The ISD-300A1 will STALL any vendor specific request if not configured by the USB host (USB configuration is 0). Label ...
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... Simple Command Queuing In simple command queuing the ISD-300A1 stops when there is a phase error and does not process a queued CBW. But when there is a device error the ISD-300A1 continues and processes the queued command the host to notice the " ...
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... Test Mode operation, all outputs not associated directly with USB operation are controllable. Normal state machine and register control of output pins are disabled. Control of the select ISD-300A1 IO pins and their 3-state controls are mapped to the USB data packet associated with this request. (See Table 13 – ...
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... DD[15:0] 3-State Active hi 3-state buffer enable for ATA data bus. DD[7:0] DD[15:8] GPIO[7:0] GPIO[9:8] GPIO[5:0] 3-State Enable Active hi 3-state buffer enable for each GPIO pin GPIO[9:6] 3-State Enable Active hi 3-state buffer enable for each GPIO pin Reserved, software must write 0000b 26 ISD-300A1 ...
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... October 19, 2001 READ_MFG_DATA This USB request returns a “snapshot in time” of select ISD-300A1 input pins. The input pin states are bit- wise mapped to the USB data packed associated with this request. ISD-300A1 input pins not associated directly with USB operation can be sampled at any time during normal or Manufacturing Test Mode operation. This request is independent of normal ISD-300A1 state machine control or Manufacturing Test Mode write operations. See Table 14 – ...
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... In the cases of USB reset and MSC reset, a partial initialization is performed which excludes all attempts to perform Identify Device commands. In the case of a Vendor-specific Soft reset, only the internal ISD-300A1 state machines are reset. Device Requirements Attached mass storage devices must support the following: ...
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... October 19, 2001 ATA Initialization Timeout ISD-300A1 internal ROM has a default configuration value of 8.2 seconds for ATA Initialization Timeout. When I_MODE operation is utilized, the default ATA Initialization Timeout value is used to retrieve FBh data. Once the vendor specific Identify (FBh) command completes, the default value is overridden with the FBh data value ...
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... October 19, 2001 ATA Command Block ATA commands for the ISD-300A1 are supported by command encoding in the command block portion of the MSC Command Block Wrapper (CBW). Refer to the USB Mass Storage Class (MSC) Bulk Only Transport Specification for information on CBW formatting. The ATA Command Block (ATACB) provides a means of passing ATA commands and ATA register accesses for execution ...
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... October 19, 2001 Bit 5 DEVOverride – Use the DEV value specified in the ATACB The DEV bit value will be determined from ISD-300A1 Configuration data (0x5 bit 5). 1= The DEV bit value will be determined from the ATACB(0xB bit 4). Bits 4-3 DPErrorOverride(1:0) - Device and Phase Error Override. These bits shall not be set in conjunction with bmATACBActionSelect TaskFileRead ...
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... ATACB Address offset 6h ATACB Address offset 7h ATACB Address offset 8h ATACB Address offset 9h ATACB Address offset Ah ATACB Address offset Bh ATACB Address offset Ch (3F6h) Device Control (1F1h) Features (1F2h) Sector Count (1F3h) Sector Number (1F4h) Cylinder Low (1F5h) Cylinder High (1F6h) Device (1F7h) Command 32 ISD-300A1 ...
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... October 19, 2001 ATA Command Flow Figure 3 shows the flow of ATA commands, specifically the actions taken by the ISD-300A1 based upon how the ATA Command Block is configured. Command Fail OR other command block specification assumed ATACB set PollAltStat Override clear Poll ATA Alternate Status until BSY=0 and store ERR and DRQ bits ...
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... ERR Read ATA Status to clear INTRQ and ignore results B Fail yes no TransferLength > Set ByteCount = (BlockSize*512) Set TransferLength = TransferLength - (BlockSize*512 ISD-300A1 page set clear set clear ATACB DPErrorOverride (1) clear ERR Read ATA Status to clear INTRQ and ignore results Read ERR Register Done ...
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... October 19, 2001 Vendor-Specific ATA Commands There are two vendor-specific ATA commands implemented in the ISD-300A1. These commands are shown in Table 16. Label IDENTIFY EVENT_NOTIFY Table 16 – Vendor-Specific ATA Commands IDENTIFY The vendor-specific Identify (FBh) command enables the ISD-300A1 to request configuration and USB descriptor information from an attached mass storage device. ...
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... When the command is issued, the device sets the BSY bit to one, and prepares to transfer 512 bytes of configuration/descriptor data to the ISD-300A1. Note: Configuration and descriptor information is limited to 256 bytes in length. Data beyond 256 bytes (bytes 256-511) is read by the ISD-300A1 but ignored. The device then sets DRQ to one and clears BSY to zero. ...
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... Note that a USB reset from the host may interrupt the collection of data. The device must accommodate the potential for this occurrence. Status register – BSY shall be cleared to zero upon command completion. DRQ shall be cleared to zero N/A N/A N/A NSTATE0 NSTATE1 N/A BSY N/A N/A N/A DRQ 37 ISD-300A1 N/A N/A N/A ...
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... Self-Powered – VBUS current is limited to 100 mA or less. • Bus-Powered – VBUS current is limited to 500 mA or less. The ISD-300A1 dynamically operates in a self or bus powered system depending upon the state of the VBUS_POWERED input. Control Pins VBUS_POWERED Pin The VBUS_POWERED input pin indicates the amount of system current drawn from VBUS. The VBUS powered input is used to qualify: • ...
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... This input pin indicates the attached device is powered and ready to begin communication with the ISD- 300A1. DISK_READY qualifies the start of the ISD-300A1’s initialization sequence. A state change from DISK_READY will cause the ISD-300A1 to wait for 25 ms before asserting NATA_RESET and re-initialize the device. The ATA interface state machines remain inactive and all of the ATA interface signals are driven logic ‘ ...
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... VBUS_SUSPEND state for the ATA interface ATA_HIZ. All ATA interface signals are 3-stated (hi-Z VBUS_SUSPEND state for ATA interface. This is a Hybrid powered application (= 1) (VBUS powered ISD-300A1, brick powered ATA/ATAPI device VBUS_SUSPEND state for the ATA interface OPERATIONAL. VBUS / Brick powered normal operation mode Notes: (1) DRV_PWR_VALID is active (polarity is correct disabled by configuration data. Table 21 – ...
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... Interrupt pipe. If the ISD-300A1 has no pending interrupt data to return, USB interrupt pipe data requests are NAK’d. If pending data is available, the ISD-300A1 returns 16-bits of data indicating the state of the GPIO[9:0] and DISK_READY pins. Table 22 and Figure 4 depicts the bit map and latching algorithm incorporated by the ISD-300A1 ...
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... The ATA_EN pin allows ATA bus sharing with other host devices. Asserting ATA_EN low causes the ISD-300A1 to 3-state all ATA bus interface pins hi-Z and suspend ATA state machine activity, otherwise leaving the ISD-300A1 operational (USB operation continues). Asserting ATA_EN high resumes normal operation ...
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... GPIO[1] Skip Identify GPIO[0] Mode 2 – XCVR signal IHSDRVON CDRCLKEN CLK_30 CLK_60 LPBACK1 LPBACK0 LOCK IOST1 IOST0 HSRCVEN 0 PWRDOWN_XCVR 43 ISD-300A1 Mode 3 – Mode 4 – XCVR signal XCVR signal TXREADY PUE TXVALID CLRXVM TXDIN(0) CLRSVP TXDIN(1) CLRXISE0 TXDIN(2) CLRSDATA TXDIN(3) CNEN TXDIN(4) ...
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... October 19, 2001 Limbo Mode This mode of operation is provided to aid debug in manufacturing environments. The ISD-300A1 3-states (high Z) all output pins during Limbo mode operation with the exception of the XO pin. The XO pin output cell does not have 3-state control (always enabled), and thus must be disabled / disconnected by other means ...
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... ATA Interface Considerations 1K Ohm Pull-down Resistor On DD<7> For “slave” devices ohm pull-down resistor must be utilized on DD7 for ISD-300A1 based designs. This is required for proper operation of the ISD-300A1 master/slave device auto detection algorithm. If this modification is omitted, slave devices will take an excessive amount of time to initialize (around 30 seconds) ...
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... In systems where the ATA/ATAPI device remains powered during ISD-300A1 low power operation (such as USB suspend state), the system design must insure the ISD-300A1 3.3V supply is not “back powered” through IO cell leakage current from the device’s 5V ATA interface, raising the supply rail above safe operating limits ...
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... OH V 3.0 DD33 = – Idle 180 mA (typ – Active < 200 mA (typ – Idle 121 mA (typ – Active < 135 mA (typ) DD 90mA (typ) 2.7 mA (typ) < 20 µA (typ ISD-300A1 Typ Max Unit 0.8 V V 0.4 V V 3.3 3.3 3.6 V ...
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... Table 27 – Memory Device Interface Timing 2 C “slow mode” specification implementation T high T low T T HD:DAT SU:DAT Symbol T high T low T HD:STA T SU:STA T HD:DAT T SU:DAT T SU:STO T DSU T BUF 48 ISD-300A1 T SU:STO T BUF Value 5066 ns 5066 ns 5066 ns 5066 ns 5066 ns 5066 ns 5066 ns 500 ns 5066 ns ...
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... All output signals are clocked using the chip’s internal system clock, for which there is no external reference. Thus, the output signals should be considered asynchronous. The PIO mode used for data register accesses is retrieved from the device or specified in the ISD-300A1 configuration bytes. Clock Crystal KDS AT-49 crystal, 10pf load capacitance ...
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... October 19, 2001 Physical Diagrams Figure 8 – Package Outline Diagram 50 ISD-300A1 ...
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... Enable APM with the register value during the drive initialization process. Setting APM Value to 0x00 disables this functionality. This register value is ignored with ATAPI devices. Time in 128 millisecond granularity before the ISD-300A1 stops polling the ALT STAT register for reset complete and restarts the reset process (0x80 = 16.4 seconds). ...
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... ATAPI device 1 ATA device or possible device initialization failure. Bit(2) Force USB full speed only operation. Setting this bit prevents the ISD-300A1 from negotiating HS operation during USB reset events 0 Normal operation – allow HS negotiation during USB reset 1 USB FS only – do not allow HS negotiation during USB reset Bit(1) Vendor Specific / MSC SOFT_RESET control ...
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... Device must be set’1’ in conjunction with Skip ATA/ATAPI Device Initialization and ATA Translation Enable. Software must issue an INQUIRY command followed with a MSC reset to allow the ISD-300A1 to parse drive information and optimize system performance and operation. Force ATA Device should be set ‘0’ for devices that support ISD-300A1 device initialization algorithms ...
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... Use timing information acquired from the Drive 1 Override device timing information with configuration values Bit (2) Enable for the DRV_PWR_VALID pin. Drive Power Valid should only be enabled in cable applications where the ISD-300A1 is VBUS powered. 0 pin disabled (most systems) 1 pin enabled Bit(1) PIO data read 3-state control. Enabling this will 3-state (hi-Z) the ATA data bus during PIO read operations while addressing the data register. In most applications this bit is set to ‘ ...
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... Enable ATAPI device UDMA support Bits(2:0) ROM UDMA Mode indicates the highest UDMA mode supported by the product. The ISD-300A1 will utilize the lesser of ROM UDMA Mode or the highest mode supported by the device. Note: UDMA read operation mode timing is controlled by the device. ...
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... Device release number in BCD msb (silicon release number). NOTE: This field entry is always returned from internal ROM contents, regardless of the descriptor source. Index to manufacturer string. This entry must equal half of the address value where the string starts the string does not exist. 56 ISD-300A1 Example SROM Data 0x23 0x00 ...
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... Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The ISD-300A1 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02 Index to the configuration string ...
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... C memory device / internal ROM space for address pointer alignment USB Interface Descriptor (FS) Length of interface descriptor in bytes. Descriptor type. Interface number. Alternate settings Number of endpoints Interface class. Interface subclass. Interface protocol. 58 ISD-300A1 Example SROM Data 0xF9 0x09 0x04 0x00 0x00 0x03 0x08 0x06 ...
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... Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The ISD-300A1 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02 Index to the configuration string ...
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... Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The ISD-300A1 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02 Index to configuration string ...
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... USB String Descriptor (Serial Number) Descriptor length Descriptor Type 61 ISD-300A1 Example SROM Data 0x00 0x6E 0x00 0x28 0x03 0x55 0x00 0x53 0x00 0x42 ...
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... Unused I C memory device space 62 ISD-300A1 Example SROM Data 0x30 0x00 0x31 0x00 0x32 0x00 0x33 0x00 0x34 0x00 0x35 ...