ISD-300A1 Cypress Semiconductor Corp, ISD-300A1 Datasheet - Page 32

• Manufacturer Part Number: ISD-300A1
• Description: IC USB 2.0 BRIDGE BULK 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of ISD-300A1

• Applications: USB 2.0 to ATA/ATAPI Bridge
• Interface: ATA, ATAPI
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1459

October 19, 2001
READ_MFG_DATA
This USB request returns a “snapshot in time” of select ISD-300A1 input pins. The input pin states are bit-
wise mapped to the USB data packed associated with this request. ISD-300A1 input pins not associated
directly with USB operation can be sampled at any time during normal or Manufacturing Test Mode
operation. This request is independent of normal ISD-300A1 state machine control or Manufacturing Test
Mode write operations. See Table 14 – READ_MFG_DATA Data Block Bit Map for an explanation of
the READ_MFG_DATA data packet format.
Legal values for wValue are as follows:
Legal values for wLength are as follows:
Table 14 shows the bit-wise input pin mapping of the data packet associated with the READ_MFG_DATA
vendor specific USB command. All input and bi-directional pin values are taken from the pin.
Table 14 – READ_MFG_DATA Data Block Bit Map
Byte
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
2
2
2
2
2
3
4
5
6
6
6
7
7
7
7
0x0000
0x0001 –
0x0008
Bit(s)
3:2
4:3
7:5
7:0
7:0
7:0
1:0
7:3
4:0
0
1
2
3
3
5
6
7
0
1
4
5
6
7
0
1
2
2
5
6
7
wValue must be set to 0x0000.
Any data packet lengths greater than 0x0008 will result in a STALL condition.
DRV_PWR_VALID
VBUS_PWR_VALID
VBUS_POWERED
DISK_READY
SYS_IRQ
IORDY
DMARQ
I_MODE
NCART_DET
N_EJECT
NLED[1:0]
NPRW500 (output register value only)
NATA_RESET (output register value only)
NDIOW (output register value only)
NDIOR (output register value only)
NDMACK (output register value only)
ATA_PU_EN (output register value only)
ATA_PD_EN (output register value only)
NCS[1:0] (output register value only)
DA[2:0] (output register value only)
DD[7:0]
DD[15:8]
GPIO[7:0]
GPIO[9:8]
DD[15:0] 3-State Control (internal register)
GPIO[4:0] 3-State Control (internal register)
GPIO[9:5] 3-State Control (internal register)
MFG_SEL (manufacturing test mode enable)
NLOWPWR (output register value only)
ATA_EN
27
Pin Name
ISD-300A1