ISD-300A1 Cypress Semiconductor Corp, ISD-300A1 Datasheet - Page 54

• Manufacturer Part Number: ISD-300A1
• Description: IC USB 2.0 BRIDGE BULK 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of ISD-300A1

• Applications: USB 2.0 to ATA/ATAPI Bridge
• Interface: ATA, ATAPI
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1459

October 19, 2001
SYS_IRQ Interface Timing
The timing specifications for SYS_IRQ relative to the USB interrupt pipe data are given below.
Figure 7 – SYS_IRQ Interface Timing
Table 28 – SYS_IRQ Interface Timing
All input signals on the ATA/ATAPI port are considered asynchronous, and are synchronized to the chip’s
internal system clock. All output signals are clocked using the chip’s internal system clock, for which there
is no external reference. Thus, the output signals should be considered asynchronous. The PIO mode used
for data register accesses is retrieved from the device or specified in the ISD-300A1 configuration bytes.
Clock
Note: Clock signal frequency is measured at V
Table 29 – Clock Requirements
Reset
The ISD-300A1 requires an off-chip power-on reset circuit. NRESET must be held asserted for a
minimum of 1 ms after power is stable.
ATA/ATAPI Port Timing Characteristics
Crystal
KDS AT-49 crystal, 10pf load capacitance.
INPUT PIN
SYS_IRQ Parameter
Interrupt pipe data set up time
SYS_IRQ hold time
Interrupt pipe data hold time
SYS_IRQ
T
SU:DAT
DD33
/2 point. Rise and fall times should be 2 ns or less.
49
T
30 MHz ± 0.005%
T
HD:DATA
HD:IRQ
Frequency
T
Symbol
T
T
HD:DATA
SU:DAT
HD:IRQ
Duty Cycle
150 ns
150 ns
n/a
Value
0 ns
ISD-300A1