ISD-300A1 Cypress Semiconductor Corp, ISD-300A1 Datasheet - Page 58

• Manufacturer Part Number: ISD-300A1
• Description: IC USB 2.0 BRIDGE BULK 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of ISD-300A1

• Applications: USB 2.0 to ATA/ATAPI Bridge
• Interface: ATA, ATAPI
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1459

October 19, 2001
Address
0x8
0x9
0xA
Initialization Status
Force ATA Device
Skip ATA / ATAPI Device
Initialization
Obsolete
Last LUN Identifier
ATA_EN
Obsolete
SRST Enable
ATA Data Assert
ATA Data Recover
Field Name
Bit (7) – read only
Drive Initialization Status
If set, indicates the drive initialization sequence state machine is active
Bit (6)
Allows software to manually enable ATA Translation with devices that do
not support ISD-300A1 device initialization algorithms. Note: Force ATA
Device must be set’1’ in conjunction with Skip ATA/ATAPI Device
Initialization and ATA Translation Enable. Software must issue an
INQUIRY command followed with a MSC reset to allow the ISD-300A1
to parse drive information and optimize system performance and
operation. Force ATA Device should be set ‘0’ for devices that support
ISD-300A1 device initialization algorithms.
Bit (5)
Skip_Init – This bit should be cleared for I_MODE
driver must initialize the attached device (if required) when this bit is set.
Note:For ATAPI devices, if Skip_Init is set the host driver must issue an
IDENTIFY command utilizing ATACBs to allow the ISD-300A1 to parse
drive information to optimize system performance and operation. Refer to
bmATACBActionSelect in the ATA Command Block - Field
Descriptions section on page 30 for further information.
0
1
Bit (4:3) – Shall be set to ‘0’
Bits (2:0)
Maximum number of LUNs device supports.
Bits (7) – read only.
Current logic state of the ATA_EN pin
Bit (6:1) – Should be set to 0
Bit (0)
SRST reset during drive initialization. Setting this bit enables the SRST
reset algorithm in the drive initialization state machines.
Bits (7:4)
Standard values for ATA compliant devices and a 30.0 MHz system clock
(in binary). Note: These values are only valid when the Override PIO
Timing configuration bit is set.
mode 0
mode 1
mode 2
mode 3
mode 4
Bits (3:0)
ATA cycle times are calculated using Data Assert and Data Recover
values. Standard recover values and cycle times for ATA compliant
devices and a 30.0 MHz system clock (in binary). Note: These values are
only valid when the Override PIO Timing configuration bit is set.
mode 0
mode 1
mode 2
mode 3
mode 4
normal operation
only reset the device and write the device control register prior to
processing commands.
0101
0011
0011
0010
0010
1100
0111
0011
0010
0000
(5+1)*33.33 = 200 ns
(3+1)*33.33 = 133 ns
(3+1)*33.33 = 133 ns
(2+1)*33.33 = 100 ns
(2+1)*33.33 = 100 ns
(4+1)+(12+1)*33.33 = 600 ns
(3+1)+(7+1)*33.33 = 400 ns
(2+1)+(3+1)*33.33 = 233 ns
(2+1)+(2+1)*33.33 = 200 ns
(2+1)+(0+1)*33.33 = 133 ns
53
Description
operation.
The host
ISD-300A1
Example
SROM
Data
0x00
0x01
0x20