hd64338342hw Renesas Electronics Corporation., hd64338342hw Datasheet - Page 186

• Manufacturer Part Number: hd64338342hw
• Description: Renesas 8-bit Single-chip Microcomputer H8 Family/h8/300l Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Power-Down Modes
2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode
A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by
executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are
both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
The time from execution of the SLEEP instruction to the end of interrupt exception handling (the
direct transition time) is given by equation (2) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
Example: Direct transition time = (2 + 1) 16tosc + 14
Notation:
tosc: OSC clock cycle time
tcyc: System clock ( ) cycle time
3. Time for direct transition from subactive mode to active (high-speed) mode
A direct transition from subactive mode to active (high-speed) mode is performed by executing a
SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in
SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1
in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (3) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
Example: Direct transition time = (2 + 1) 8tw + (8192 + 14)
Notation:
tosc:
tw:
tcyc:
tsubcyc: Subclock (
Rev. 6.00 Aug 04, 2006 page 150 of 680
REJ09B0145-0600
the CPU operating clock)
OSC clock cycle time
Watch clock cycle time
System clock ( ) cycle time
w/8 is selected as the CPU operating clock, and wait time = 8192 states)
SUB
processing states) }
exception handling execution states)
processing states) }
STS2 to STS0) + (number of interrupt exception handling execution
states) }
) cycle time
(tcyc after transition)
(tcyc before transition) + (number of interrupt
(tsubcyc before transition) + { (wait time set in
2tosc = 76tosc (when /8 is selected as
(tcyc after transition)
2tosc = 24tw + 16412tosc (when
.................................. (2)
........................ (3)