cbtl06dp211 NXP Semiconductors, cbtl06dp211 Datasheet - Page 6

• Manufacturer Part Number: cbtl06dp211
• Description: Cbtl06dp211 Displayport Gen1 2 1 Multiplexer
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 2.
7. Functional description
CBTL06DP211
Product data sheet
Symbol
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
AUX+
AUX−
HPD_1
HPD_2
HPDIN
VDD
GND
Pin description
7.1 Multiplexer/switch select functions
Ball
H8
J8
H5
J5
H2
H1
J2
H3
J1
A2, J4
B3, C8,
G8, H4,
H7
Refer to
The CBTL06DP211 uses a 3.3 V power supply. All main signal paths are implemented
using high-bandwidth pass-gate technology and are non-directional. No clock or reset
signal is needed for the multiplexer to function.
The switch position for the main channels is selected using the select signal GPU_SEL.
Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the
DDC / AUX channel. The detailed operation is described in
The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and
DDC_AUX_SEL as described below.
Table 3.
Table 4.
GPU_SEL
0
1
GPU_SEL
0
1
…continued
Type
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
single-ended I/O
single-ended I/O
single-ended I/O
power supply
ground
Figure 1 “Functional
Multiplexer/switch select control for IN and OUT channels
Multiplexer/switch select control for HPD channel
All information provided in this document is subject to legal disclaimers.
IN1_n
active; connected to OUT_n
high-impedance
HPD1
active; connected to HPDIN
high-impedance
Rev. 1 — 21 February 2011
Description
Pair of single-ended terminals for DDC clock and data signals,
path 1, left-side.
Pair of single-ended terminals for DDC clock and data signals,
path 2, left-side.
High-speed differential pair for AUX or single-ended DDC signals,
right-side.
Single ended channel for the HPD signal, path 1, left-side.
Single ended channel for the HPD signal, path 2, left-side.
Single ended channel for the HPD signal, right-side.
3.3 V power supply.
Ground.
diagram”.
DisplayPort Gen1 2 : 1 multiplexer
IN2_n
high-impedance
HPD2
high-impedance
active; connected to OUT_n
active; connected to HPDIN
CBTL06DP211
Section
7.1.
© NXP B.V. 2011. All rights reserved.
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