mk5025q-1002 STMicroelectronics, mk5025q-1002 Datasheet - Page 22

• Manufacturer Part Number: mk5025q-1002
• Description: High Speed Link Level Controller
• Manufacturer: STMicroelectronics

MK50H25
4.1.2.4 Control and Status Register 3 (CSR3)
RAP<3:1> = 3
4.1.2.5 Control and Status Register 4 (CSR4)
CSR4 allows redefinition of the bus master interface.
RAP<3:1> = 4
22/64
07:00
BIT
15:00
BIT
15:12 XWD0/1, RWD0/1
11
10
NAME
ROBA
XHOLD
IADR
NAME
IADR
1
5
X
W
D
1
1
5
1
4
1
4
X
W
D
0
1
3
The high order 8 bits of the address of the first word (lowest address)
in the Initialization Block. IADR must be written by the Host prior to
issuing an INIT primitive.
The low order 16 bits of the address of the first word (lowest address)
in the Initialization Block. Must be written by the Host prior to issuing
an INIT primitive. The Initialization block must begin on an even byte
boundary.
DESCRIPTION
These bits enable and determine the timer values for the Transmit and
Receive Watchdog Timers. These timers are independently program-
mable and are reset by any transition on the TCLK and RCLK pins re-
spectively. The Watchdog timers will expire after approximately Wn
SYSCLK cycles (if not reset by transition on TCLK / RCLK pins) and
Provider Primitive 3 will be issued. The following table shows the se-
lections for Wn:
Setting this bit will cause the MK50H25 to put the first byte of received
data into both the upper and lower bytes of the receive buffer to effec-
tively cause the Receive data to be Odd-Byte Aligned. This feature is
particularly useful for extraction of odd-byte Level 3 headers from re-
ceived frames leaving the remaining data even byte aligned.
Setting this bit enables the Transmit FIFO Hold-off mechansim of the
MK50H25. The Transmit FIFO Hold-off watermark is selected along
with the FIFO watermark so as to avoid possible conflicts.
XWD1/RWD1
R
W
D
1
1
3
DESCRIPTION
1
2
1
2
R
W
D
0
0
0
1
1
1
1
1
1
R
O
B
A
1
0
IADR <15:00>
X
H
O
L
D
1
0
0
9
0
9
M
F
W
XWD0/RWD0
0
8
0
8
0
7
0
7
B
A
E
0
1
0
1
0
6
0
6
B
U
S
R
0
5
0
5
B
S
W
P
C
0
4
B
U
R
S
T
0
4
Disabled
0
3
0
:
1
0
3
2
2
2
Wn
18
19
20
0
2
B
S
W
P
D
0
2
0
1
A
C
O
N
0
1
0
0
B
C
O
N
0
0
0