mk5025q-1002 STMicroelectronics, mk5025q-1002 Datasheet - Page 54

• Manufacturer Part Number: mk5025q-1002
• Description: High Speed Link Level Controller
• Manufacturer: STMicroelectronics

Figure 8: MK50H25 BUS Master Timing Diagram (Write) (for CYCLE = 0, CSR2<15>)
DAL0-15
SYSCLK
A 16-23
READY
HOLD
HLDA
DALO
BM0,1
READ
DALI
ALE
DAS
NOTES:
2. Output delay times are the maximum delay from the specifed edge to a valid output.
3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments
1. The shaded SYSCLK periods T0 and T5 will be removed when setting CSR2 bit 15,
CYCLE =1 to select the shorter DMA cycle as shown in Figure 8a.
until the slave device returns READY.
24
64
45
27
23
23
T 0
25
29
T 1
ADDR
33
T 2
40
T 3
ADDRESS
60
43
34
T 4
44
DATA
T 5
61
T 6
28
26
41
65
MK50H25
42
22
35
48
48
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