isd5100 Winbond Electronics Corp America, isd5100 Datasheet - Page 48

• Manufacturer Part Number: isd5100
• Description: Single-chip 1 To 16 Minutes Duration Voice Record/playback Devices With Digital Storage Capability
• Manufacturer: Winbond Electronics Corp America

SCL (Serial Clock Line)
The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor
to Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged
over the Serial Data Line.
SDA (Serial Data Line)
The Serial Data Line carries the data between devices on the I
this line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is
a bi-directional line requiring a pull-up resistor to Vcc.
RAC (Row Address Clock)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency,
the duration of this period is 256 ms. RAC stays HIGH for 248 ms and stays LOW for the remaining 8
ms before it reaches the end of a row. There are 2048 rows of memory in the ISD5116 devices, 1024
rows in the ISD5108, 512 rows in the ISD5104 and 256 rows in the ISD5102.
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing
mode. See the
rates. When a record command is first initiated, the RAC pin remains HIGH for an extra T
to load sample and hold circuits internal to the device. The RAC pin can be used for message
management techniques.
7.6. P
During 8 KHz Operation
During Message Cueing
7.6.1. Digital I/O Pins
@ 8KHz Operation
RAC Waveform
IN
RAC Waveform
D
ETAILS
Timing Parameters table
on page 64 for RAC timing information at other sample
- 48 -
500 usec
256 msec
T
1 ROW
RACM
T
RAC
1 ROW
2
C interface. Data must be valid on
ISD5100 SERIES
15.6 us
T
RACML
8 msec
T
RACL
RACML
period,