ne5900n NXP Semiconductors, ne5900n Datasheet - Page 4

• Manufacturer Part Number: ne5900n
• Description: Call Progress Decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
At the start of an in-band tone (envelope output goes high), a 2.3
second interval is timed out. Transitions of the envelope during this
interval are counted to determine the signal present. At 2.3
seconds, the three bits of data representing this decision are stored
in the latch and appear at the outputs. A data valid signal goes high
at this time, signaling that the data bits, Pins 10 – 12, can be read.
The output code is as follows:
The overflow condition occurs in the event that too many transitions
occur during the 2.3 second interval. This can result from noise,
voice, or other line disturbances not normally present during the
Figure 4 shows a typical application of the call progress decoder.
In this application only one external component is needed an no
microprocessor activity other than clear is required.
Figure 5 shows the recommended direct interface to the telephone
line. Bus connection is possible by utilizing tri-state, and internal
timing is accomplished with a 3.58MHz crystal.
1986 May 8
Dial Tone
Ringing Signal
Busy Signal
Re-order Tone
Overflow
Call progress decoder
EXT CLOCK
PROGRESS
DATA VALID
COUNT IN
IN/XTAL1
IN/XTAL2
CLEAR
INPUT
IN
Pin 12
0
1
0
0
1
OSCILLATOR
2.3 SECOND
ANTI-ALIAS
DIVIDERS
3.58MHz
CLOCK
FILTER
TIMER
Pin 11
0
0
1
0
1
Figure 3. Detailed Block Diagram CPD
Pin 10
0
0
0
1
1
SC BANDPASS
DECODER
DECODER
LOWPASS
LATCHES
FILTER
FILTER
LOGIC
4
post-dialing interval. Note that the end of dial tone in interpreted as
a valid ringing signal.
The clear input resets all internal registers and the output latch, and
is to be set low after the completion of dialing. The clear input
should be pulsed high for proper operation. Recommended pulse
width is between 0.2 s and 20ms. If clear is held high when
envelope is high, a false output pulse (Pin 13) can result when clear
is returned low.
For applications where dialing is done by a person rather than by a
microprocessor, an uncertainty exists about the number of digits to
be dialed (local vs long distance). In such situations it is possible to
clear the NE5900 by application of the DTMF signal or dial pulses to
the clear pin (Pin 6). When dialing is complete, the device is cleared
and ready to respond to the next call progress unit.
Enable is held at 5V to enable Pins 10, 11, 12 and 13. When enable
is brought low, data valid is also set low. Enable must remain high
while the data is also set low. Enable must remain high while the
data is being read. The test pin is for production test only and must
be kept low in all user applications.
The designer can utilize the input signal, clock, bus, or
microprocessor interface which best serves the application. Figure
6 gives a typical timing diagram for the application of Figures 4 and
5.
DETECTOR
DETECTOR
TRI-STATE
BUFFERS
ANALOG
DIGITAL
BUFFER
R1
R2
10k
10k
Product specification
NE5900
V
TRI-STATE
ENABLE
ENVELOPE
BIT 1
BIT 2
BIT 3
5V
0V
REF
SR01144