cx24118a NXP Semiconductors, cx24118a Datasheet - Page 23

• Manufacturer Part Number: cx24118a
• Description: Advanced Modulation Digital Satellite Tuner
• Manufacturer: NXP Semiconductors

3.1
Figure 5.
CX24118A_N_2
Product data sheet
FOOTNOTE:
(1)
(2)
Acknowledge generated by CX24118A.
Subsequent bytes are assumed to be data for registers whose addresses follow in ascending order.
SDA
SCL
Serial Programming Interface
Typical Single-Byte Write Procedure
Serial Clock and Data Signals
1
The CX24118A uses an I
and SDA, are used to transfer data at a clock rate of up to 1 MHz. A direct, exclusive
connection is preferred between controlling master and the tuner slave. If the chip is put on a
common I
interference. Both lines operate on 3.3 V I/O voltage levels. The SDA line is open drain,
requiring an external pull-up resistor.
The serial clock and data signals for a typical transaction is shown in
The START condition occurs on the falling edge of the SDA line when the SCL line is held
high. A STOP condition occurs on the rising edge of the SDA line when the SCL line is held
high. Every data word is 8 bits long with MSB first, followed by an acknowledge bit generated
by the receiving device. Each data transaction occurs between a START and a STOP
condition. The START condition is followed by a slave address. If this is the CX24118A
address, it generates an acknowledge bit on the SDA line.
The following are some typical read/write sequences:
The above-described single-byte write procedure is shown in
In the figure, the following abbreviations are used:
CX24118A
Chapter 3: Serial Programming Interface and Registers
Rev. 02 — 8 September 2009
1.
2.
3.
4.
5.
2
S = Start
Dev Addr/wr = Device address with a write command
A = Acknowledge
P = Stop
Send the Start condition.
Send the CX24118A slave address, a write bit, and receive an ACK.
Send the CX24118A desired register address = n, and receive an ACK.
Send the byte for a desired register = n, and receive an ACK.
Send the Stop condition.
3
Address
4
Slave
2
C bus shared by other devices, the ongoing traffic on the bus may cause RF
5
6
7
(1)
8
Rev. 02 — 8 September 2009
9
2
1
C-compatible serial interface. The serial clock and data lines, SCL
2
3
Register
Address
4
5
6
7
(1)
8
9
1
2
3
4
Figure
Data
5
6
(2)
Product data sheet
6.
Figure
7
8
© NXP B.V. 2009. All rights reserved.
9
5.
102322_012
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