74abt16374b NXP Semiconductors, 74abt16374b Datasheet - Page 2

• Manufacturer Part Number: 74abt16374b
• Description: 16-bit D-type Flip-flop; Positive-edge Trigger 3-state
• Manufacturer: NXP Semiconductors

The 74ABT16374B has two 8-bit, edge triggered registers, with each
high-impedance “OFF” state, which means they will neither drive nor
DESCRIPTION
The 74ABT16374B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
register coupled to eight 3-State output buffers. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-LOW Output Enable (nOE) controls all eight 3-State buffers
for its register independent of the clock operation.
When nOE is LOW, the stored data appears at the outputs for that
register. When nOE is HIGH, the outputs for that register are in the
load the bus.
QUICK REFERENCE DATA
ORDERING INFORMATION
T
Philips Semiconductors
amb
Type number
74ABT16374BB
74ABT16374BDGG
74ABT16374BDL
2004 Mar 08
SYMBOL
16-bit D-type flip-flop; positive-edge trigger
(3-State)
C
I
t
t
I
C
PLH
PHL
CCZ
CCL
= –40 C to +85 C
OUT
IN
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Quiescent supply current
Quiescent supply current
Package
Name
QFP52
TSSOP48
SSOP48
PARAMETER
Description
plastic quad flat package; 52 leads (lead length 1.6 mm); body 10
plastic thin shrink small outline package; 48 leads; body width 6.1 mm
plastic shrink small outline package; 48 leads; body width 7.5 mm
2
FEATURES
C
V
V
Outputs disabled; V
Outputs LOW; V
Two 8-bit positive edge triggered registers
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
Multiple V
3-State output buffers
Output capability: +64 mA/–32 mA
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
I
O
L
= 0 V or V
= 50 pF; V
= 0V or V
T
amb
CC
CONDITIONS
= 25 C; GND = 0 V
CC
CC
CC
and GND pins minimize switching noise
; 3-State
CC
= 5 V
CC
= 5.5 V
= 5.5 V
10
74ABT16374B
2.0 mm
TYPICAL
500
2.6
2.2
4
7
8
Version
SOT379-1
SOT362-1
SOT370-1
Product data
UNIT
mA
pF
pF
ns
A