w25q32bw Winbond Electronics Corp America, w25q32bw Datasheet
w25q32bw
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w25q32bw Summary of contents
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... SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: March 13, 2009 - 1 - Preliminary - Revision B W25Q32BW ...
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... Erase/Program Suspend Status (SUS) 10.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0) 10.1.10 Quad Enable (QE) 10.1.11 Status Register Memory Protection (CMP = 0) 10.1.12 Status Register Memory Protection (CMP = 1) Table of Contents ............................................................................................................... 5 ................................................................................... 6 ........................................................................................ 6 ............................................................................................ 7 .................................................................................................. 7 ..................................................................................................................... 8 .................................................................................................................. 8 ............................................................................................................... 8 ..................................................................................................................... 8 ................................................................................................................ 8 ....................................................................................................... 10 ............................................................................................................. 10 .....................................................................................................10 ............................................................................................................10 ..........................................................................................................10 .......................................................................................................................10 ....................................................................................................... 11 .........................................................................................................11 ........................................................................................ 12 .......................................................................................................... 12 ..................................................................................................12 ....................................................................................12 ...........................................................................................12 ................................................................................................12 ...............................................................................................13 ..............................................................................13 ..............................................................................13 ............................................................................................................ W25Q32BW .................................................... 6 .................................... 8 ..............................................................13 .................................................................15 .................................................................16 ...
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... Erase Security Registers (44h) 10.2.37 Program Security Registers (42h) 10.2.38 Read Security Registers (48h ) 11. ELECTRICAL CHARACTERISTICS ................................................................................................................. 17 ..............................................................................17 ........................................................................19 .............................................................................................................21 .............................................................................................................21 ................................................................................................23 .................................................................................................................24 ...............................................................................................................25 ...........................................................................................26 ..........................................................................................27 .................................................................................................28 ...............................................................................................30 ..............................................................................................32 .....................................................................................34 ................................................................................................36 .................................................................................37 .........................................................................................................38 ......................................................................................39 ...........................................................................................................40 ...................................................................................................41 ...................................................................................................42 .....................................................................................................43 .......................................................................................44 .......................................................................................45 ............................................................................................................46 .........................................................................................47 ...............................................................................49 ........................................................................................52 ......................................................................................................53 .........................................................................................54 ....................................................................................55 ........................................................................................56 .............................................................................................. W25Q32BW ........................................................18 ..............................................................20 .......................................22 ................................................................37 ..............................................................47 .................................................................50 ...............................................................51 Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... SOIC 150-mil (Package Code SN) 12.2 8-Pin SOIC 208-mil (Package Code SS) 12.3 8-Contact 6x5mm WSON (Package Code ZP) 12.4 16-Pin SOIC 300-mil (Package Code SF) 13. ORDERING INFORMATION 13.1 Valid Part Numbers and Top Side Marking 14. REVISION HISTORY ...................................................................................................................... 71 ................................................................................................ 57 .............................................................................................................. 57 .................................................................... 58 .............................................................................................. 59 ............................................................................................. 60 .............................................................................................. 61 ................................................................................. 62 ........................................................................................................... 63 .......................................................................................................... 64 ........................................................................... 64 ........................................................................... 65 .................................................................. 66 .......................................................................... 68 .......................................................................................................... 69 ........................................................................ W25Q32BW ...
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... Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q32BW has 1,024 erasable sectors and 64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage ...
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... PIN CONFIGURATION SOIC 150 / 208-MIL Figure 1a. W25Q32BW Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN & SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25Q32BW Pad Assignments, 8-pad WSON (Package Code ZP) 5. PIN DESCRIPTION SOIC 150 / 208-MIL, AND WSON 6X5-MM PIN NO. PIN NAME ...
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... PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25Q32BW Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME 1 /HOLD (IO3) 2 VCC 3 N/C 4 N/C 5 N/C 6 N (IO1) 9 /WP (IO2) 10 GND 11 N/C 12 N/C 13 N (IO0) 16 CLK *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – ...
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... Package Types W25Q32BW is offered in an 8-pin plastic150-mil width SOIC (package type SN), an 8-pin plastic 208-mil width SOIC (package code SS) and a 6x5-mm WSON (package code ZP) as shown in figure 1a and 1b, respectively also offered in a 16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1c ...
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... SPI /CS /CS Command & Command & Control Logic Control Logic DI ( ( Figure 2. W25Q32BW Serial Flash Memory Block Diagram xxFFFFh xxFFFFh • • xxF0FFh xxF0FFh xxEFFFh xxEFFFh • • xxE0FFh xxE0FFh xxDFFFh xxDFFFh • • xxD0FFh xxD0FFh ...
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... Dual SPI Instructions The W25Q32BW supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP) ...
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... One Time Program (OTP) write protection * Note: This feature is available upon special order. Please refer to the Ordering Information. Upon power- power-down, the W25Q32BW will maintain a reset condition while VCC is below the threshold value (See Power-up Timing and Voltage Levels and Figure 37). While reset, all WI operations are disabled and no instructions are recognized ...
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... The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC= W25Q32BW , ...
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... When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and can not be written to again until the next power-down, power-up cycle. Status Register is permanently protected and can not be (2) written to. Publication Release Date: March 13, 2009 - 13 - W25Q32BW (1) Preliminary - Revision B ...
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... Figure 3a. Status Register-1 S15 S15 S14 S14 S13 S13 SUS SUS CMP CMP LB3 LB3 (non-volatile) (non-volatile) (non-volatile) (non-volatile) (non-volatile) (non-volatile ) Figure 3b. Status Register W25Q32BW BP2 BP2 BP1 BP1 BP0 BP0 WEL BUSY WEL BUSY S12 S12 S11 ...
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... X Note don’t care Lower Upper W25Q32BW (32M-BIT) MEMORY PROTECTION PROTECTED PROTECTED BLOCK(S) ADDRESSES NONE NONE 63 3F0000h – 3FFFFFh 62 and 63 3E0000h – 3FFFFFh 60 thru 63 3C0000h – 3FFFFFh 56 thru 63 380000h – 3FFFFFh 48 thru 63 300000h – 3FFFFFh 32 thru 63 200000h – ...
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... X Note don’t care Lower Upper W25Q32BW (32M-BIT) MEMORY PROTECTION PROTECTED PROTECTED BLOCK(S) ADDRESSES ALL 000000h – 3FFFFFh 0 thru 62 000000h – 3EFFFFh 0 and 61 000000h – 3DFFFFh 0 thru 59 000000h – 3BFFFFh 0 thru 55 000000h – 37FFFFh 0 thru 47 000000h – ...
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... INSTRUCTIONS The instruction set of the W25Q32BW consists of thirty four basic instructions that are fully controlled through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first ...
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... A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 dummy dummy dummy FFh - 18 - W25Q32BW (1) BYTE 4 BYTE 5 BYTE 6 A7–A0 (D7–D0) (3) A7–A0 (D7–D0, …) A7–A0 A7–A0 A7–A0 ...
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... A23-A0, M7-M0 (D7-D0, …) (4) xxxxxx, W6-W4 Set Burst with Wrap Input IO0 = W4, x IO1 = W5, x IO2 = IO3 = Publication Release Date: March 13, 2009 - 19 - W25Q32BW BYTE 4 BYTE 5 BYTE 6 A7-A0 (D7-D0) A7-A0 dummy (D7-D0) A7-A0 dummy (D7-D0, …) A7-A0 dummy (D7-D0, … ...
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... A23-A8 A7-A0, M[7:0] A23-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF7-MF0) (ID15-ID8) Manufacturer Memory Type dummy dummy A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15– W25Q32BW BYTE 4 BYTE 5 (1) dummy (ID7-ID0) 00h (MF7-MF0) (ID7-ID0) (MF[7:0], ID[7:0]) (MF[7:0], ID[7:0], …) (ID7-ID0) Capacity dummy dummy (ID63-ID0) A7–A0 A7–A0 (D7-0) A7– ...
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... Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 4. Write Enable Instruction Sequence Diagram Figure 5. Write Disable Instruction Sequence Diagram - 21 - W25Q32BW Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram - 22 - W25Q32BW ...
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... After the Write Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. Please refer to 10.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits are 0. Figure 7. Write Status Register Instruction Sequence Diagram Publication Release Date: March 13, 2009 - 23 - W25Q32BW (See AC W Preliminary - Revision B ...
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... The Read Data instruction sequence is shown in figure Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D. maximum of f (see AC Electrical Characteristics). Figure 8. Read Data Instruction Sequence Diagram - 24 - W25Q32BW R ...
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... The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”. Figure 9. Fast Read Instruction Sequence Diagram - 25 - W25Q32BW Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... The input data during the dummy clocks is “don’t care”. However, the IO out clock. Figure 10. Fast Read Dual Output Instruction Sequence Diagram and IO . This allows data to be transferred from the W25Q32BW pin should be high-impedance prior to the falling edge of the first data 0 ...
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... Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q32BW at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of F Electrical Characteristics). This is accomplished by adding eight “ ...
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... A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 10.2.19 for detail descriptions). Figure 12a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 10 W25Q32BW ...
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... Figure 12b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) Publication Release Date: March 13, 2009 - 29 - W25Q32BW Preliminary - Revision B ...
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... Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 10.2.19 for detail descriptions). Figure 13a. Fast Read Quad I/O Instruction Sequence Diagram (Initial Fast Read Quad I/O instruction or previous The Quad I/O dramatically reduces instruction overhead . - 30 - W25Q32BW and IO and four Dummy 2 3 Byte 1 Byte 1 Byte 2 Byte 2 ...
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... The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See 10.2.17 for detail descriptions. Publication Release Date: March 13, 2009 - 31 - W25Q32BW Preliminary - Revision B ...
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... Byte 1 Byte 1 Byte 2 Byte 2 W25Q32BW Byte 3 ...
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... Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Publication Release Date: March 13, 2009 - 33 - W25Q32BW Preliminary - Revision B ...
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... Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte W25Q32BW Byte 4 Byte 4 ...
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... Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Publication Release Date: March 13, 2009 - 35 - W25Q32BW Preliminary - Revision B ...
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... Wrap instruction should be issued to set The default value of W4 upon power the case of a system Reset while recommended that the controller issues a Set Burst with Wrap instruction to reset prior to any normal Read instructions since W25Q32BW does not have a hardware Reset Pin. ...
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... Figure 17. Continuous Read Mode Reset for Fast Read Dual/Quad I/O Since W25Q32BW does not have a hardware Reset pin the controller resets while W25Q32BW is set to Continuous Mode Read, the W25Q32BW will not recognize any initial standard SPI instructions from the controller. To address this possibility recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a system Reset ...
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... After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits. Figure 18. Page Program Instruction Sequence Diagram - 38 - W25Q32BW ...
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... Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in figure 19. Figure 19. Quad Input Page Program Instruction Sequence Diagram , and IO . The Quad Page Program can Publication Release Date: March 13, 2009 - 39 - W25Q32BW Preliminary - Revision B ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Sector Erase SE Figure 20. Sector Erase Instruction Sequence Diagram - 40 - W25Q32BW ...
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... Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 21. 32KB Block Erase Instruction Sequence Diagram 1 (See AC Characteristics). While the Block Erase BE Publication Release Date: March 13, 2009 - 41 - W25Q32BW Preliminary - Revision B ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 22. 64KB Block Erase Instruction Sequence Diagram (See AC Characteristics). While the Block Erase cycle W25Q32BW ...
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... Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Chip Erase cycle is in progress, CE Figure 23. Chip Erase Instruction Sequence Diagram - 43 - W25Q32BW Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted recommended for the users to implement system design techniques against the accidental power interruption and preserve data integrity during the erase/program suspend state. Figure 24. Erase/Program Suspend Instruction Sequence - 44 - W25Q32BW ...
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... Resume instructions will be ignored unless an Erase/Program Suspend operation is active. Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off. Figure 25. Erase/Program Resume Instruction Sequence Publication Release Date: March 13, 2009 - 45 - W25Q32BW Preliminary - Revision B ...
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... This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 26. Deep Power-down Instruction Sequence Diagram - 46 - W25Q32BW ...
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... The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 28a. The Device ID values for the W25Q32BW is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. ...
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... Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle. Figure 28a. Release Power-down/High Performance Mode Instruction Sequence Figure 28b. Release Power-down / Device ID Instruction Sequence Diagram (See AC Characteristics). After this time duration the device will RES2 - 48 - W25Q32BW ...
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... Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 29. The Device ID values for the W25Q32BW is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... CLK with most significant bits (MSB) first as shown in figure 30. The Device ID values for the W25Q32BW is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other ...
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... ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in figure 31. The Device ID values for the W25Q32BW is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q32BW device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Read JEDEC ID (9Fh) For compatibility reasons, the W25Q32BW provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Erase Security Registers (44h) The W25Q32BW offers four 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1) ...
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... Figure 35. Program Security Registers Instruction Sequence A23-16 A15-12 00h 00h 00h 00h Publication Release Date: March 13, 2009 - 55 - W25Q32BW A11-8 A7 Byte Address Byte Address Byte Address Byte Address Preliminary - Revision B ...
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... Instruction (48h) Instruction (48h) Figure 36. Read Security Registers Instruction Sequence A23-16 A15-12 00h 00h 00h 00h W25Q32BW A11-8 A7 Byte Address Byte Address Byte Address Byte Address ...
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... Electrostatic Discharge Voltage Notes: 1. Specification for W25Q32BW is preliminary. See preliminary designation at the end of this document. 2. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. ...
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... Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. SYMBOL MIN t (1) VSL t (1) PUW V (1) 1.0 WI Figure 37. Power-up Timing and Voltage Levels - 58 - W25Q32BW SPEC UNIT MAX 1.4 µ ...
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... DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open /CS = VCC /CS = VCC /CS = VCC /CS = VCC –0.5 VCC x 0 100 µA OL VCC – 0 –100 µA OH Publication Release Date: March 13, 2009 - 59 - W25Q32BW SPEC UNIT TYP MAX ±2 µA ±2 µ µ µA 50 100 µ ...
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... Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL Figure 38. AC Measurement I/O Waveform - 60 - W25Q32BW SPEC UNIT MIN MAX 0.2 VCC to 0.8 VCC V 0.3 VCC to 0.7 VCC V 0.5 VCC to 0.5 VCC V ...
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... SHSL CSH ( SHQZ DIS CLQV CLQV CLQX HLCH Publication Release Date: March 13, 2009 - 61 - W25Q32BW SPEC UNIT TYP MAX 80 MHz 50 MHz ns ns V/ Continued – next page Preliminary - Revision B ...
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... RES (2) t SUS t W (4) t BP1 (4) t BP2 BPN BP1 + BP2 * W25Q32BW SPEC ALT MIN TYP MAX 100 2.5 10 0.7 30 200 120 800 150 1,000 5 15 ...
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... Serial Output Timing 11.9 Input Timing 11.10 Hold Timing Publication Release Date: March 13, 2009 - 63 - W25Q32BW Preliminary - Revision B ...
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... Formed leads shall be planar with respect to one another within .0004 inches at the seating plane. MILLIMETERS TYP. MAX MIN 1.60 1.72 0.058 --- 0.24 0.004 1.45 --- --- 0.41 0.50 0.013 0.20 0.25 0.0075 4.85 4.95 0.189 6.00 6.19 0.228 3.90 4.00 0.150 1.27 BSC 0.71 1.27 0.015 o o --- 8 0 --- 0.10 --- - 64 - W25Q32BW INCHES TYP. MAX 0.063 0.068 --- 0.009 0.057 --- 0.016 0.020 0.008 0.0098 0.191 0.195 0.236 0.244 0.154 0.157 0.050 BSC 0.028 0.050 o --- 8 --- 0.004 ...
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... Formed leads shall be planar with respect to one another within .0004 inches at the seating plane. MILLIMETERS INCHES MIN MAX MIN 1.75 2.16 0.069 0.05 0.25 0.002 1.70 1.91 0.067 0.35 0.48 0.014 0.19 0.25 0.007 5.18 5.38 0.204 7.70 8.10 0.303 5.18 5.38 0.204 1.27 BSC 0.050 BSC 0.50 0.80 0.020 --- 0.10 --- Publication Release Date: March 13, 2009 - 65 - W25Q32BW MAX 0.085 0.010 0.075 0.019 0.010 0.212 0.319 0.212 0.031 8 o 0.004 Preliminary - Revision B ...
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... MILLIMETERS MIN TYP. MAX 0.70 0.75 0.80 0.0276 0.00 0.02 0.05 0.0000 0.55 0.19 .0.20 0.25 0.0075 0.36 0.40 0.48 0.0138 5.90 6.00 6.10 0.2320 3.30 3.40 3.50 0.1299 4.90 5.00 5.10 0.1930 4.20 4.30 4.40 0.1653 1.27 BSC 0.20 0.0080 0.50 0.60 0.75 0.0197 - 66 - W25Q32BW INCHES MIN TYP. MAX 0.0295 0.0315 0.0008 0.0019 0.0126 0.0080 0.0098 0.0157 0.0190 0.2360 0.2400 0.1338 0.1377 0.1970 0.2010 0.1692 0.1732 0.0500 BSC 0.0236 0.0295 ...
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... The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad. MILLIMETERS MIN TYP. MAX 3.40 4.30 6.00 0.50 0. W25Q32BW INCHES MIN TYP. MAX 0.1338 0.1692 0.2360 0.0196 0.0255 Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. MILLIMETERS INCHES MIN MAX MIN 2.36 2.64 0.093 0.10 0.30 0.004 0.33 0.51 0.013 0.18 0.28 0.007 10.08 10.49 0.397 10.01 10.64 0.394 7.39 7.59 0.291 1.27 BSC 0.050 BSC 0.39 1.27 0.015 --- 0.076 --- - 68 - W25Q32BW MAX 0.104 0.012 0.020 0.011 0.413 0.419 0.299 0.050 8 o 0.003 ...
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... Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 2b. For shipments with OTP feature enabled, please specify when placing orders. (1) W 25Q 8-pad WSON 6x5mm SF = 16-pin SOIC 300-mil Publication Release Date: March 13, 2009 - 69 - W25Q32BW ( Preliminary - Revision B ...
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... Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the W25Q32BW SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 11- digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 9-digit number ...
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... Added Set Burst with Wrap Opcode 77h 69 & 70 Modified Continuous Read Mode Bit settings Updated Ordering Information 20, 54~56 Added Security Register 0 Note. 69 Add note 2b. 32,33 Typo M6 pin to QE bit Important Notice - 71 - W25Q32BW DESCRIPTION New Create Preliminary ranteed. Winbond Publication Release Date: March 13, 2009 Preliminary - Revision B ...