m36w432b STMicroelectronics, m36w432b Datasheet - Page 20

• Manufacturer Part Number: m36w432b
• Description: 32 Mbit 2mb X16, Boot Block Flash Memory And 4 Mbit 256k X16 Sram, Multiple Memory Product
• Manufacturer: STMicroelectronics

M36W432T, M36W432B
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended. When the Program
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command. The Program Suspend Status
should only be considered valid when the Pro-
gram/Erase Controller Status bit is High (Program/
Erase Controller inactive). Bit 2 is set within 5µs of
the Program/Erase Suspend command being is-
sued therefore the memory may still complete the
operation rather than entering the Suspend mode.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Table 10. Status Register Bits
Note: Logic level '1' is High, '0' is Low.
SRAM Operations
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable, WS, is at V
put Enable, GS, is at V
20/57
Bit
7
6
5
4
3
2
1
0
P/E.C. Status
Erase Suspend Status
Erase Status
Program Status
V
Program Suspend Status
Block Protection Status
Reserved
PPF
Status
IL
, Chip Enable, E1S, is at
Name
IH
, Out-
Logic Level
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.
Note: Refer to Appendix C, Flowcharts and
Pseudo Codes, for using the Status Register.
V
UBS and LBS are at V
Valid data will be available on the output pins after
a time of t
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t
er than the address. Data out may be indetermi-
nate at t
will always be valid at t
13 and 14).
IL
, Chip Enable, E2S, is at V
new
E1LQX
AVQV
Ready
Busy
Suspended
In progress or Completed
Erase Error
Erase Success
Program Error
Program Success
V
V
Suspended
In Progress or Completed
Program/Erase on protected block, Abort
No operation to protected blocks
PPF
PPF
command
, t
after the last stable address. If the
Invalid, Abort
OK
E2HQX
E1LQV
AVQV
IL
and t
.
Definition
will
, t
(see Table 19, Figures
E2HQV
IH
GLQX
, and Byte Enables,
appear
, or t
, but data lines
GLQV
to
) rath-
fail.