m36w432b STMicroelectronics, m36w432b Datasheet - Page 7

• Manufacturer Part Number: m36w432b
• Description: 32 Mbit 2mb X16, Boot Block Flash Memory And 4 Mbit 256k X16 Sram, Multiple Memory Product
• Manufacturer: STMicroelectronics

Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at V
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at V
can be locked or unlocked. (refer to Table 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RPF). The Reset input provides a
hardware reset of the Flash memory. When Reset
is at V
are high impedance and the current consumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at V
in normal operation. Exiting reset mode the device
enters read array mode, but a negative transition
of Chip Enable or a change of the address is re-
quired to ensure valid data outputs.
SRAM Chip Enable (E1S, E2S). The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S at V
E2S at V
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
SRAM memory array, while WS remains at V
is not allowed to set EF at V
at V
SRAM Write Enable (WS). The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM memory. GS is ac-
tive low.
SRAM Upper Byte Enable (UBS). The
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS is active low.
SRAM Lower Byte Enable (LBS). The
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS is active low.
IH
IL
IH
at the same time.
, the memory is in reset mode: the outputs
, the Lock-Down is disabled and the block
IL
deselects the memory and reduces the
IL,
E1S at V
IH
, the device is
IL
and E2S
IL
Upper
Lower
IH
, the
IL.
or
It
V
vides the power supply to the internal core of the
Flash Memory device. It is the main power supply
for all operations (Read, Program and Erase).
V
V
memory I/O pins and V
supply for the SRAM control pins. This allows all
Outputs to be powered independently from the
Flash core power supply, V
to V
V
control input and a power supply pin for the Flash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Volt-
age V
can be applied in any order.
If V
V
age lower than V
against program or erase, while V
ables these functions (see Table 14, DC Charac-
teristics for the relevant values). V
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase op-
erations continue.
If V
power supply pin. In this condition V
stable until the Program/Erase algorithm is com-
pleted (see Table 16 and 17).
V
ground reference for all voltage measurements in
the Flash and SRAM chips, respectively.
Note: Each device in a system should have V
DF
pacitor close to the pin. See Figure 9, AC
Measurement Load Circuit. The PCB trace
widths should be sufficient to carry the re-
quired V
DDF
DDQF
DDQF
PPF
PPF
SSF
, V
PPF
PPF
DDS
DDQF
is seen as a control input. In this case a volt-
Supply Voltage (2.7V to 3.3V). V
Program Supply Voltage. V
and V
DDF
and V
is kept in a low voltage range (0V to 3.6V)
provides the power supply for the Flash
is in the range 11.4V to 12.6V it acts as a
PPF
and the Program Supply Voltage V
and V
SSS
program and erase currents.
DDS
Ground. V
PPLK
PPF
Supply Voltage (2.7V to 3.3V).
decoupled with a 0.1µF ca-
M36W432T, M36W432B
gives an absolute protection
DDS
DDF
SSF
provides the power
. V
and V
DDQF
PPF
PPF
PPF
PPF
> V
SSS
can be tied
is both a
DDF
PPLK
must be
is only
are the
pro-
7/57
PPF
en-
D-