lh28f128bfht-pbtl75a Sharp Microelectronics of the Americas, lh28f128bfht-pbtl75a Datasheet - Page 5

• Manufacturer Part Number: lh28f128bfht-pbtl75a
• Description: Flash Memory 16mbit 8mbitx16
• Manufacturer: Sharp Microelectronics of the Americas

The product, which is 6-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low
power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can
operate at V
The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus
eliminating time consuming wait states.
The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main
Blocks that provide maximum flexibility for safe nonvolatile code and data storage.
Fast program capability is provided through the use of high speed Page Buffer Program.
Special OTP (One Time Program) block provides an area to store permanent code such as an unique number.
* ETOX is a trademark of Intel Corporation.
• 75/25ns 8-Word Page Mode
• Read operations are available during Block Erase or
• Plane Architecture:
• 2.7V Read and Write Operations
• V
• Automatic Power Savings Mode reduces I
• 5µs Typical Erase/Program Suspends
• 4-Word Factory-Programmed Area
• 4-Word User-Programmable Area
• 16-Word Page Buffer
• 5µs/Word (Typ.) at WP#/ACC=9.5V
128-M density with 16-bit I/O Interface
High Performance Reads
6-Plane Dual Work Operation
Low Power Operation
Enhanced Code + Data Storage
OTP (One Time Program) Block
High Performance Program with Page Buffer
Operating Temperature -40°C to +85°C
CMOS Process (P-type silicon substrate)
(Page Buffer) Program between two different Planes
16M, 24M, 24M, 24M, 24M, 16M
in Static Mode
CCQ
for Input/Output Power Supply Isolation
CC
=2.7V-3.3V. Its low voltage operation capability greatly extends battery life for portable applications.
Page Mode Dual Work Flash MEMORY
LH28F128BFHT-PBTL75A
128Mbit (8Mbit×16)
CCR
LHF12F17
• Eight 4-Kword Parameter Blocks
• Two-hundred and fifty-five 32-Kword Main Blocks
• Bottom Parameter Location
• Individual Block Lock and Block Lock-Down with
• All blocks are locked at power-up or device reset.
• Block Erase, Full Chip Erase, (Page Buffer) Word
• 3.0V Low-Power 11µs/Word (Typ.)
• 9.5V No Glue Logic 9µs/Word (Typ.)
• Basic Command Set
• Common Flash Interface (CFI)
• Minimum 100,000 Block Erase Cycles
Flexible Blocking Architecture
Enhanced Data Protection Features
Automated Erase/Program Algorithms
Cross-Compatible Command Support
Extended Cycling Capability
56-Lead TSOP (Normal Bend)
ETOX
Not designed or rated as radiation hardened
Zero-Latency
Program Lockout during Power Transitions
Programming
Production Programming and 0.8s Erase (Typ.)
TM*
Flash Technology
Rev. 0.04
2