hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 28

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.2
Read and write accesses to the DDR2 SDRAM are
burst oriented; accesses start at a selected location
and continue for the burst length of four or eight in a
programmed sequence.
Accesses begin with the registration of an Activate
command, which is followed by a Read or Write
command. The address bits registered coincident with
the activate command are used to select the bank and
row to be accessed.
3.3
DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below
2. Start clock (CK, CK) and maintain stable power and
Figure 8
Data Sheet
CK, CK
CKE
ODT "low"
0.2 ×
may be undefined). To guarantee ODT off,
must be valid and a low level must be applied to the
ODT pin. Maximum power up interval for
is specified as 20.0 ms. The power interval is
defined as the amount of time it takes for
to power-up from 0 V to 1.8 V ± 100 mV. At least
one of these two sets of conditions must be met:
–
converter output, AND
–
–
or
– Apply
– Apply
– Apply
V
clock condition for a minimum of 200 µs.
REF
NOP
V
V
V
DD
TT
REF
.
,
V
is limited to 0.95 V max, AND
V
400 ns
DDQ
tracks
DDL
V
V
V
Basic Functionality
Power On and Initialization
Initialization Sequence after Power up
DD
DDL
DDQ
and ODT at a low state (all other inputs
and
PRE
ALL
before or at the same time as
before or at the same time as
before or at the same time as
V
DDQ
tRP
V
DDQ
EMRS(2)
/2
are driven from a single power
tMRS
EMRS(3)
tMRS
with DLL enable
Register(1) Set
Extended
EMRS(1)
Mode
tMRS
V
V
DLL reset
Register
Set with
MRS
Mode
DD
DD
V
V
tMRS
V
V
DDL.
/
/
REF
DDQ.
TT
V
V
DDQ
DDQ
&
PRE
ALL
28
tRP
The address bits registered coincident with the Read or
Write command are used to select the starting column
location for the burst access and to determine if the
Auto-Precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register
definition, command description and device operation.
3. Apply NOP or Deselect commands and take CKE
4. Continue NOP or Deselect Commands for 400 ns,
5. Issue EMRS(2) command.
6. Issue EMRS(3) command.
7. Issue EMRS(1) command to enable DLL.
8. Issue a MRS command for “DLL reset”.
9. Issue Precharge-all command.
10. Issue 2 or more Auto-refresh commands.
11. Issue the final MRS command to turn the DLL on
12. At least 200 clocks after step 8, issue EMRS(1)
13. The DDR2 SDRAM is now ready for normal
min. 200 cycles to lock the DLL
1st Auto
refresh
high.
then issue a Precharge All command.
and to set the necessary operating parameter.
commands to either execute the OCD calibration or
select the OCD default. Issue the final EMRS(1)
command to exit OCD calibration mode and set the
necessary operating parameters.
operation.
tRFC
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
2nd Auto
refresh
tRFC
DLL reset
Register
Set w/o
MRS
Mode
tMRS
OCD Drive(1)
OCD default
EMRS(1)
OCD
or
512-Mbit DDR2 SDRAM
Follow OCD
flowchart
Functional Description
09112003-SDM9-IQ3P
calibration
mode exit
EMRS(1)
OCD
OCD
Rev. 1.3, 2005-01
tMRS
Command
Any