hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 35

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hyb18t512160af-5

Manufacturer Part Number
hyb18t512160af-5
Description
512-mbit Ddr2 Sdram
Manufacturer
Infineon Technologies Corporation
Datasheet
3.11
The Extended Mode Register EMR(3) is reserved for
future use and all bits except BA0 and BA1 must be
programmed to 0 when setting the mode register during
Table 12
Field
BA2
BA1
BA0
A
1) w = write only
Data Sheet
Bits
16
15
14
[13:0] w
Extended Mode Register EMR(3)
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010
Type
reg.addr
1)
Description
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
0
Bank Adress[1]
1
Bank Adress[0]
1
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0
B
B
B
B
BA2, Bank Address
BA1, Bank Address
BA0, Bank Address
A[13:0], Address bits
35
initialization. The EMRS(3) is written by asserting low
on CS, RAS, CAS, WE, BA2 and high on BA0 and BA1,
while controlling the state of the address pins.
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
B
09112003-SDM9-IQ3P
)
Rev. 1.3, 2005-01

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