s-24cs16a Seiko Instruments Inc., s-24cs16a Datasheet - Page 18
s-24cs16a
Manufacturer Part Number
s-24cs16a
Description
2-wire Cmos Serial E2prom
Manufacturer
Seiko Instruments Inc.
Datasheet
1.S-24CS16A.pdf
(46 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
s-24cs16a01
Manufacturer:
SEIKO
Quantity:
1 463
Part Number:
s-24cs16a01-J8T1GE
Manufacturer:
SEIKO/精工
Quantity:
20 000
Company:
Part Number:
s-24cs16a0I-H6T3
Manufacturer:
SEIKO
Quantity:
38 162
Part Number:
s-24cs16a0I-I8T1G
Manufacturer:
SEIKO/精工
Quantity:
20 000
Part Number:
s-24cs16a0I-J8T1
Manufacturer:
SEIKO
Quantity:
20 000
Part Number:
s-24cs16a0I-J8T1G
Manufacturer:
SII/精工
Quantity:
20 000
Company:
Part Number:
s-24cs16a0I-J8T1GE
Manufacturer:
SEIKO
Quantity:
4 608
Part Number:
s-24cs16a0I-J8T1GE
Manufacturer:
SEIKO
Quantity:
20 000
Company:
Part Number:
s-24cs16aOI-J8T1G
Manufacturer:
SHARP
Quantity:
3 677
18
LINE
SDA
2-WIRE CMOS SERIAL E
S-24CS16A
ADDRESS
7. 3 Sequential Read
DEVICE
When the E
start condition both in current and random read operations, it responds with an acknowledge.
An 8-bit data is then sent from the E
incremented at the falling edge of the SCL clock for the 8th bit data.
When the master device responds with an acknowledge, the data at the next memory address is transmitted.
Response with an acknowledge by the master device has the memory address counter in the E
incremented and makes it possible to read data in succession. This is called “Sequential Read”.
The master device outputs stop condition not an acknowledge, the reading of E
Data can be read in succession in the sequential read mode. When the memory address counter reaches the last
word address, it rolls over to the first memory address.
W
R
D
R
E
A
1
/
C
A
K
2
D7
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a
DATA (n)
2
PROM
ADR INC
D0
A
C
K
2
PROM synchronous to the SCL clock and the address counter is automatically
D7
Figure 19 Sequential Read
Seiko Instruments Inc.
DATA (n+1)
ADR INC
D0
A
C
K
D7
DATA (n+2)
2
ADR INC
PROM is ended.
D0
C
A
K
D7
Master Device
NO ACK from
DATA (n+x)
Rev.5.1
ADR INC
D0
2
PROM
00
O
S
P
T