psd4235g2 STMicroelectronics, psd4235g2 Datasheet - Page 37

• Manufacturer Part Number: psd4235g2
• Description: Flash In-system Programmable Isp Peripherals For 16-bit Mcus 5v Supply
• Manufacturer: STMicroelectronics

PSD4235G2
Table 29.
1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label
2. All values are in hexadecimal:
3. Only address bits A11-A0 are used in instruction decoding.
4. All WRITE bus cycles in an instruction are byte WRITE to an even address (XA4Ah or X554h). A Flash memory Program
5. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active high, and are defined in PSDsoft Express.
6. No Unlock or instruction cycles are required when the device is in the READ mode.
7. The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active,
READ
Read Main Flash ID
Read Sector
Protection
(9)
Program a Flash
Word
Flash Sector
Erase
Flash Bulk Erase
Suspend Sector
Erase
Resume Sector
Erase
Reset
Unlock Bypass
Unlock Bypass
Program
Unlock Bypass
Reset
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses, RA = Address of the memory
location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR,
CNTL0). PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to
be erased, or verified, must be Active (High).
bus cycle writes a word to an even address.
Protection Status, or if the Error Flag bit (DQ5/DQ13) goes high.
and (A1,A0)=(1,0)
Instruction
(9)
(10)(9)
(11)
(12)
(7)
(14)
(6)
(13)
(7)(8)
Instructions
(4)
(9)
(7)
CSBOOT3
FS0-FS7 or
CSBOOT0-
(1)(2)(3)
1
1
1
1
1
1
1
1
1
1
1
1
(5)
“Read”
RD @ RA
AAh@
XAAAh
AAh@
XAAAh
AAh@
XAAAh
AAh@
XAAAh
AAh@
XAAAh
B0h@
XXXXh
30h@
XXXXh
F0h@
XXXXh
AAh@
XAAAh
A0h@
XXXXh
90h@
XXXXh
Cycle 1
55h@
X554h
55h@
X554h
55h@
X554h
55h@
X554h
55h@
X554h
55h@
X554h
PD@ PA
00h@
XXXXh
Cycle 2
90h@
XAAAh
90h@
XAAAh
A0h@
XAAAh
80h@
XAAAh
80h@
XAAAh
20h@
XAAAh
Cycle 3
Read ID
@ XX02h
Read 00h
or 01h @
XX04h
PD@ PA
AAh@
XAAAh
AAh@
XAAAh
Cycle 4
55h@
X554h
55h@
X554h
Cycle 5
Detailed operation
30h@
SA
10h@
XAAAh
Cycle 6
30h
@ next
SA
Cycle 7
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(10)