mt28f640j3rp-115-met Micron Semiconductor Products, mt28f640j3rp-115-met Datasheet - Page 37

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mt28f640j3rp-115-met

Manufacturer Part Number
mt28f640j3rp-115-met
Description
128mb, 64mb, 32mb Q-flash Memory
Manufacturer
Micron Semiconductor Products
Datasheet
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
Figure 15: CLEAR BLOCK LOCK BITS
FULL STATUS CHECK PROCEDURE
Read Status Register
CLEAR BLOCK LOCK
CLEAR BLOCK LOCK
Data (see above)
Check if Desired
BITS Successful
BITS Complete
Read Status
Full Status
Write D0h
Write 60h
Register
SR4,5 =
SR3 =
SR7 =
SR5 =
Start
1
0
0
0
Flowchart
0
1
1
1
Voltage Range Error
Command Sequence
CLEAR BLOCK LOCK
BITS Error
Error
37
BUS
OPERATION
WRITE
WRITE
READ
STANDBY
Write FFh after the CLEAR BLOCK LOCK BITS operation to place
device in read array mode.
BUS
OPERATION
STANDBY
STANDBY
STANDBY
SR5, SR4, and SR3 are only cleared by the Clear Status Register
command.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COMMAND
COMMAND
CLEAR BLOCK
CLEAR BLOCK
CONFIRM
LOCK BITS
SETUP
LOCK BITS
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
COMMENTS
Check SR3
1= Programming Voltage
Check SR4, SR5
Both 1 = Command
Check SR4
1 = Clear Block Lock Bits
Error
COMMENTS
Data = 60h
Addr = X
Data = D0h
Addr = X
Status Register Data
Check SR7
1 = ISM Ready
0 = ISM Busy
Error Detect
Sequence Error
©2000 Micron Technology. Inc.

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