tc58nvg0s3aft05 TOSHIBA Semiconductor CORPORATION, tc58nvg0s3aft05 Datasheet
tc58nvg0s3aft05
Available stocks
Related parts for tc58nvg0s3aft05
tc58nvg0s3aft05 Summary of contents
Page 1
... CLE 16 ALE TC58NVG0S3AFT05 x Powersupply x Program/Erase Cycles x Access time Cell array to register Serial Read Cycle x Operating current Read (50 ns cycle) Program (avg.) Erase (avg.) Standby x Package TSOPI48-P-1220-0.50 (Weight: 0.53 g typ.) PIN NAMES 48 NC I/O1 to I/O8 I/O port 47 NC ...
Page 2
... This parameter is periodically sampled and is not tested for every device. Status register Address register Command register Control circuit HV generator 0 MHz) CONDITION OUT TC58NVG0S3AFT05 Column buffer Column decoder Data register Sense amp Memory cell array VALUE UNIT 0.6 to 4.6 V 0 ...
Page 3
... OUT mA OUT cycle V 400 2 pin V 0 TC58NVG0S3AFT05 TYP. MAX UNIT 1024 Blocks TYP. MAX UNIT 3 0.8 V MIN TYP. MAX UNIT r10 r10 ...
Page 4
... RHW t WE High to CE Low WHC t WE High to RE Low WHR t CE Low to RE Low (ID Read Memory Cell Array to Starting Address High to Busy WB t Device Reset Time (Read/Program/Erase) RST TC58NVG0S3AFT05 MIN MAX UNIT NOTES ...
Page 5
... V~3 SYMBOL PARAMETER t Average Programming Time PROG Number of Programming Cycles on Same Page N (per 512 16 bytes) t Block Erasing Time BERASE (1) Refer to Application Note (12) toward the end of this document. TC58NVG0S3AFT05 CONDITION 2 1.5 V, 1.5 V 1 (100 pF TTL L MIN TYP. MAX UNIT 200 ...
Page 6
... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE CE RE Setup Time WE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE t DS I/O1 to I/O8 Hold Time CLH ALH t DH TC58NVG0S3AFT05 : 2003-08-20A 6/33 ...
Page 7
... CA8 to 11 PA0 TC58NVG0S3AFT05 ALH PA8 CLH 2111 2003-08-20A 7/33 ...
Page 8
... REH RHZ REA RHZ t CLSTO WHC CSTO t WHR TC58NVG0S3AFT05 t CEA CHZ REA RHZ t CHZ RSTO t RHZ Status output : 2003-08-20A 8/33 ...
Page 9
... CLS CLH ALH ALS PA0 to 7 PA8 to 15 30h TC58NVG0S3AFT05 t CLEA t CEA REA OUT OUT Data out from Col. Add CLEA t CEA t CHZ ...
Page 10
... ALH ALS 30h PA0 to 7 PA8 to 15 Page address P TC58NVG0S3AFT05 t CLEA t CEA REA OUT OUT OUT Page address P Column address A 1 Continues next page ...
Page 11
... Continued from 1 of last page t CLEA t t CLS CLH CEA t t ALH ALS REA OUT E0h CA8 Page address B Column address B TC58NVG0S3AFT05 D OUT OUT B N’ P 2003-08-20A 11/33 ...
Page 12
... DS DH I/O1 80h CA0 to 7 CA8 to 11 PA0 to 7 PA8 I/ ALH t ALS 2111 not input data while data is being output TC58NVG0S3AFT05 t Prog Status 10h 70h output 2003-08-20A 12/33 ...
Page 13
... ALH ALE I/O1 60h PA0 to 7 PA8 I/O8 Auto Block Erase Setup command BERASE D0h Busy Erase Start command : not input data while data is being output TC58NVG0S3AFT05 Status 70h output Status Read command 2003-08-20A 13/33 ...
Page 14
... REAID I/O 90h 00h ID Read Address command 00 Note 1: 80h or 00h Note 2: 95h or 15h Note 3: 40h or C0h t CEA ALEA t t REAID REAID 98h F1h Note 1 Maker code Device code TC58NVG0S3AFT05 t t REAID REAID Note 2 Note 2003-08-20A 14/33 ...
Page 15
... Busy state ( during the Program, Erase and Read operations and will return to Ready state ( after completion of the operation. The output buffer for this signal is an open drain and has to be pulled-up to Vccq with appropriate resister. TC58NVG0S3AFT05 ...
Page 16
... PA11 PA10 PA9 PA8 CLE ALE TC58NVG0S3AFT05 (128K 4K) bytes CA0 to CA11 : Column address PA0 to PA15 : Page address PA6 to PA15 : Block address PA0 to PA5 : NAND address in block * V 2003-08-20A 16/33 ...
Page 17
... Serial Data Input: 80h I/ TC58NVG0S3AFT05 Acceptable while Busy @ @ I/O1 to I/O8 Power Data output Active High impedance Active High impedance Standby High Impedance Active 2003-08-20A 17/33 ...
Page 18
... In the serial data out from the register, the column address can be changed by inputting the column address with 05h and E0h commands. The data are read out in serial from the column address which is input to the device by 05h and E0h commands with Cell array RE clock. TC58NVG0S3AFT05 Page Address N E0h M’ ...
Page 19
... If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. 70 Status Read command Busy TC58NVG0S3AFT05 70h Status Out Pass I/O Fail 2003-08-20A 19/33 ...
Page 20
... Descripton I/O8 I/O7 I/ level cell 4 level cell 8 level cell 16 level cell TC58NVG0S3AFT05 Note 2 Note 3 Note 1: 80h or 00h Note 2: 95h or 15h Note 3: 40h or C0h I/O2 I/O1 Hex Data 98h F1h 80h or 00h 95h or 15h ...
Page 21
... Reserved u16 Descripton I/O8 I/O7 I/ Mbit 0 0 128 Mbit 0 0 256 Mbit 0 1 512 Mbit Gbit Gbit Gbit Gbit TC58NVG0S3AFT05 I/O5 I/O4 I/O3 I/O2 I/ I/O5 I/O4 I/O3 I/O2 I/ ...
Page 22
... Fail: 1 Busy: 0 Not Protected Device 3 Busy 70h Status on Device N BY pin signals from multiple devices are wired together as shown in the TC58NVG0S3AFT05 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device ...
Page 23
... FF t (max 10 Ps) RST FF t (max 500 Ps) RST FF t (max 6 Ps) RST 70 I/O status : Pass/Fail o Pass I/O status : Ready/Busy o Busy (1) ( command is invalid, but the third FF TC58NVG0S3AFT05 Figure 8. 00 Figure 9. 00 Figure 10. 00 Figure 11. : Ready/Busy o Ready Figure 12. (3) FF command is valid. 2003-08-20A 23/33 ...
Page 24
... Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of command while Busy state During Busy state, do not input any command except 70h, and FFh max Operation Figure 15. Power-on/off Sequence FF Reset Figure 16. TC58NVG0S3AFT05 Don’t care V IL Don’t care 2003-08-20A 24/33 ...
Page 25
... Page 0 (1) Page 1 (2) Page 2 (3) Page 31 (32) Page 63 (64 Mode specified by the command. Ex.) Random page program (Prohibition) DATA IN: Data (1) Page 0 Page 1 Page 2 Page 31 Page 63 Figure 17. page programming within a block TC58NVG0S3AFT05 Programming cannot be executed. Data (64) Data register (2) (32) (3) (1) (64) 2003-08-20A 25/33 ...
Page 26
... Ready V CC 3.0 V 1.0 V Busy Figure 19. TC58NVG0S3AFT05 00 [A] Status output Status Read 80 10 Address Data N input BY buffer consists of an open drain 3 25° 100 ...
Page 27
... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE 80 DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min) WW TC58NVG0S3AFT05 2003-08-20A 27/33 ...
Page 28
... When five address cycles are input Although the device may read in a fifth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00h Program operation CLE CE WE ALE I/O 80h Ignored Address input Figure 22. Ignored Address input Figure 23. TC58NVG0S3AFT05 30h Data input 2003-08-20A 28/33 ...
Page 29
... Note: The input data for unprogrammed or previously programmed page segments must be “1” (i.e. the inputs for all page bytes outside the segment which programmed should be set to all “1”). All 1 s Data Pattern 2 All 1 s All 1 s Data Pattern 2 Figure 24. TC58NVG0S3AFT05 Data Pattern 8 Data Pattern 8 2003-08-20A 29/33 ...
Page 30
... Block No 1 Fail Read Check Pass Bad Block *1 Block No. 1024 Yes End Figure 27. TC58NVG0S3AFT05 TYP. MAX UNIT 1024 Block page of each block. If the column address 0 or 2048 of the 1st page or the 2nd page is not FF (Hex), define the block as a bad block. ...
Page 31
... Block Verify after Program o Retry (2) ECC When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, Block A prevent further system accesses to Block A (by creating a bad block table or by using another appropriate scheme). Block B Figure 28. TC58NVG0S3AFT05 2003-08-20A 31/33 ...
Page 32
... Package Dimensions Weight: 0.53 g (typ.) TC58NVG0S3AFT05 2003-08-20A 32/33 ...
Page 33
... The products described in this document are subject to the foreign exchange and foreign trade laws. x TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. TC58NVG0S3AFT05 030619EBA 2003-08-20A 33/33 ...