stc3800 Connor-Winfield VCXOs, stc3800 Datasheet - Page 22

• Manufacturer Part Number: stc3800
• Description: Integrated - Stratum 3e Timing Source
• Manufacturer: Connor-Winfield VCXOs

Register Descriptions and Operation continued
Intr_Event, 0x12 (R)
Interrupt state = 1. When an enabled interrupt occurs, the INTR pin is asserted, active low. All interrupts are cleared and the INTR
pin pulled high when the register is read. Reset default is 0.
Intr_Enable, 0x13 (R/W)
Enables or disables the corresponding interrupts from asserting the INTR pin. Interrupt events still appear in the Intr_Event register
independent of their “enable” state. Reset default is interrupts disabled.
Ref(1-8)_Frq_Offset, 0x14 ~ 0x1b (R)
These registers indicate the frequency offset, in 0.2 ppm resolution, between each reference and the local calibrated freerun clock.
0x14 - 0x1b correspond to Ref1 - Ref8.
Loss of
Lock
Enable Inter-
rupt event 7: rupt event 6:
1: Enable
0: Disable
Default: 0
2’s complement value of frequency offset between reference and calibrated local oscillator, 0.2 ppm resolution
Bit 7
Bit 7
Loss of
Enable Inter-
1: Enable
0: Disable
Default: 0
Signal
Bit 6
Bit 6
Active
change
Enable Inter-
rupt event 5:
1: Enable
0: Disable
Default: 0
Bit 5
reference
Bit 5
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Preliminary Data Sheet #: TM061
DPLL Mode
status
change
Enable Inter- Enable Inter-
rupt event 4:
1: Enable
0: Disable
Default: 0
Bit 4
Bit 4
Bit 7 ~ Bit 0
activity to
Xref Change
from no
activity
rupt event 3:
1: Enable
0: Disable
Default: 0
Bit 3
Bit 3
Xref Change
from activity
to no activity
Enable Inter-
rupt event 2:
1: Enable
0: Disable
Default: 0
Bit 2
Bit 2
Page 22 of 48
Specifications subject to change without notice
Any reference
change
from not
available to
available
Enable Inter-
rupt event 1:
1: Enable
0: Disable
Default: 0
Bit 1
Bit 1
Rev: P06
Any reference
change
from available
to not available
Enable Inter-
rupt event 0:
1: Enable
0: Disable
Default: 0
Date: 11/22/04
Bit 0
Bit 0