stc3800 Connor-Winfield VCXOs, stc3800 Datasheet - Page 5

• Manufacturer Part Number: stc3800
• Description: Integrated - Stratum 3e Timing Source
• Manufacturer: Connor-Winfield VCXOs

Pin Name
Sel0
Sel1
Sel2
Sel3
BITS_Sel
LOS
LOL
Hold_Avail
Xref
Ref1
Ref2
Ref3
Ref4
Ref5
Ref6
Ref7
Ref8
Sync_Clk
Sync_8K
BITS_Clk
Sync_2K
M_Clk
VC_TTL
VC_PPECL
VC_NPECL
VC_Sel
DACclk
DACdin
DACld
E
E
E
MNC
2
2
2
scl
sda
wp
M11, M12
G1, G4,
Pin #
G12
L10,
A10
A11
A12
C11
K12
E11
D11
B12
C12
D12
L11
F12
F11
J12
M1
M2
M3
M4
M5
M6
M7
M8
A9
H2
D1
D2
K2
K1
F1
E2
J2
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Preliminary Data Sheet #: TM061
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Pin Description
In Hardware Mode (HM_Ref = 1), Sel0 ~ Sel3 will determine the Free Run,
1.544 MHz or 2.048 MHz BITS clock selection, 1 = 1.544 MHz, 0 = 2.048 MHz
Table 1 continued
Synchronous Clock: Output frequency is dependent on VCXO frequency
Loss of signal indicator for the selected reference, 1 = Loss of Signal
Selects the input VCXO signal electrical format, 0: PECL, 1: TTL
Locked, Hold Over, and the Active Reference in Locked Mode.
See Table 5 in Hardware Control Modes section
See Table 5 in Hardware Control Modes section
See Table 5 in Hardware Control Modes section
See Table 5 in Hardware Control Modes section
Mandatory no-connect - must be left floating
OCXO or TCXO local crystal oscillator input
Hold Over history built and usable = 1
Loss of phase lock, 1 = Loss of Lock
DAC Serial Bus Interface: CS/LD
DAC Serial Bus Interface: CLK
DAC Serial Bus Interface: Din
Synchronous Clock: 8 kHz
EEPROM interface: SDA
EEPROM interface: SCL
EEPROM interface: WP
Multi-frame sync: 2 kHz
Cross Reference Input
VCXO NPECL input
VCXO PPECL input
Reference Input 1
Reference Input 2
Reference Input 3
Reference Input 4
Reference Input 5
Reference Input 6
Reference Input 7
Reference Input 8
BITS clock output
VCXO TTL input
Page 5 of 48
Description
Specifications subject to change without notice
Rev: P06 Date: 11/22/04