tza3012ahw NXP Semiconductors, tza3012ahw Datasheet - Page 21

• Manufacturer Part Number: tza3012ahw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-ratetm Fibre Optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
CHARACTERISTICS OF THE I
The I
(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Bit transfer
Refer to Fig.13. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during
the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals.
Start and stop conditions
Refer to Fig.14. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data
line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the stop condition (P).
2003 May 21
handbook, full pagewidth
handbook, full pagewidth
30 Mbits/s up to 3.2 Gbits/s
A-rate
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line
fibre optic receiver
SDA
SCL
START condition
SDA
SCL
2
S
C-BUS
Fig.14 Definition of start and stop conditions.
data valid
data line
stable;
Fig.13 Bit transfer.
21
allowed
change
of data
STOP condition
MBC621
P
MBC622
TZA3012AHW
SDA
SCL
Product specification