lm5119psqx National Semiconductor Corporation, lm5119psqx Datasheet - Page 20

• Manufacturer Part Number: lm5119psqx
• Description: Lm5119 Wide Input Range Dual Synchronous Buck Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
yond the loop crossover frequency. A good approximation of
the location of the pole added by C
C
example.
MISCELLANEOUS FUNCTIONS
EN2 is left floating which allows channel2 to always remain
enabled. If EN2 is pulled below 2V, channel2 is disabled.
The DEMB pin is left floating since this design uses diode
emulation. For fully synchronous (continuous conduction) op-
eration, connect the DEMB to a voltage greater than 2.6V.
VCCDIS is left floating to enable the internal VCC regulators.
To disable the internal VCC regulators, connect this pin to a
voltage greater than 1.25V.
INTERLEAVED OPERATION
Interleaved operation can offer many advantages in single
output, high current applications. The output power path is
split between two identical channels reducing the current in
each channel by one-half. Ripple current reduction in the out-
put capacitors is reduced significantly since each channel
operates 180 degrees out of phase from the other. Ripple re-
duction is greatest at 50% duty cycle and decreases as the
duty cycle varies away from 50%.
Refer to
Also, the effective ripple in the input and output capacitors
occurs at twice the frequency of a single channel design due
to the combining of the two channels. All of these factors are
advantageous in managing the higher currents and their ef-
fects in a high power design.
FIGURE 12. Cancellation Factor vs. Duty Cycle for Output
To begin an interleaved design, use the previous equations
in this datasheet to first calculate the required value of com-
ponents using one-half the current in the output power path.
The Attenuation Factor in
capacitor ripple to the inductor ripple vs. duty cycle. The in-
ductor ripple used in this calculation is the ripple in either
HF
. The value of C
Figure 12
HF
to estimate the ripple current reduction.
was selected as 100pF for the design
Capacitor
Figure 12
HF
is the ratio of the output
is: f
P2
= f
30124019
ZEA
x C
COMP
/
20
inductor in a two phase design, not the ripple calculated for a
single phase design of the same output power. It can be ob-
served that operation around 50% duty cycle results in almost
complete ripple attenuation in the output capacitor.
12
in the output capacitors.
Figure 13
capacitors due to interleaving. As with the output capacitors,
there is near perfect ripple reduction near 50% duty cycle.
This plot can be used to calculate the ripple in the input ca-
pacitors at any duty cycle. In designs with large duty cycle
swings, use the worst case ripple reduction for the design.
To configure the LM5119 for interleaved operation, connect
COMP1 and COMP2 pins together at the IC. Connecting the
FB2 pin to VCC2 pin will disable the channel2 error amplifier
with a high output impedance at COMP2. Connect the com-
pensation network between FB1 and the common COMP
pins. Connect the two power stages together at the output
capacitors. Finally use the plots in
along with the duty cycle range to determine the amount of
output and input capacitor ripple reduction. Frequently more
capacitance than necessary is used in a design just to meet
ESR requirements. Reducing the capacitance based solely
on ripple reduction graphs alone may violate this requirement.
In the LM5119 evaluation board (schematic shown in
14) interleaved operation can be enabled by shorting both
outputs together (with identical components in the power
train), and using zero ohm resistors for R22 and R21. This
shorts VCC2 to FB2 and COMP2 to COMP1 respectively. Al-
so the channel2 feedback network C14, R6, and C15 should
be removed. The easy re-configuration between two channel
and single channel operation will allow insight into the benefits
of interleaved operation.
FIGURE 13. Normalized Input Capacitor RMS Ripple
can be used to calculate the amount of ripple attenuation
illustrates the ripple current reduction in the input
Current vs. Duty Cycle
Figure 12
and
30124020
Figure 13
Figure
Figure