lm5119psqx National Semiconductor Corporation, lm5119psqx Datasheet - Page 22

• Manufacturer Part Number: lm5119psqx
• Description: Lm5119 Wide Input Range Dual Synchronous Buck Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
PCB Board Layout
Recommendations
The LM5119 consists of two integrated regulators operating
almost independently. Crosstalk between the two regulators
under certain conditions may be observed as switch jitter.
This effect is common for any dual channel regulator. Cross-
talk effects are usually most severe when one channel is
operating around 50% duty cycle. Careful layout practices
help to minimize this effect. The following board layout guide-
lines apply specifically to the LM5119 and should be followed
for best performance.
1.
2.
3.
4.
5.
6.
Switching Jitter Root Causes and Solutions
1.
2.
3.
Keep the Loop1 and Loop2, shown in
as possible
Keep the signal and power grounds separate
Place VCC capacitors (C6, C7) and VIN capacitor (C9)
as closes as possible to the LM5119
Route CS and CSG traces together with Kelvin
connection to the sense resistor
Connect AGND and PGND directly to the underside
exposed pad
Ensure there are no high current paths beneath the
underside exposed pad
Noise coupling of the high frequency switching between
two channels through the input power rail
A.
B.
C. Place local bypass capacitors (C
D. Slow down the SW switching speed by increasing
E.
High frequency AC noise on FB, CS, CSG and COMP
A.
B.
C. Add an R-C filter between the CS and CSG pins
D. Place CS filter capacitor (C30, C31) next to the
Ground offset at the switching frequency
A.
Keep the high current path as short as possible
Choose a FET with minimum lead inductance
as possible to the high-side FETs to isolate one
channel from the high frequency noise of the other
channel
gate resistors R29 and R30
Minimize the effective ESR/ESL of the input
capacitor by paralleling input capacitors
Use the star ground PCB layout technique and
minimize the length of the high current path
Keep the signal traces away from the SW, HO, HB
traces and the inductor
LM5119 and on the same PCB layer as the LM5119
Use the star ground PCB layout technique and
minimize the length between the grounds of C
C
IN2
Figure
IN1
, C
IN2
15, as small
) as close
IN1
and
22
FIGURE 15. Recommended PCB Layout
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