lm5119psqx National Semiconductor Corporation, lm5119psqx Datasheet - Page 4

• Manufacturer Part Number: lm5119psqx
• Description: Lm5119 Wide Input Range Dual Synchronous Buck Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
Pin
EP
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RAMP2
PGND2
Name
CSG2
VCC2
UVLO
SW2
HO2
HO1
SW1
CS2
HB2
HB1
LO2
VIN
EP
Description
PWM ramp signal. An external resistor and capacitor connected between the SW2 pin, the RAMP2
pin and the AGND pin sets the channel2 PWM ramp slope. Proper selection of component values
produces a RAMP2 signal that emulates the current in the buck inductor.
Current sense amplifier input. Connect to the high side of the channel2 current sense resistor.
Kelvin ground connection to the external current sense resistor. Connect directly to the low side of
the channel2 current sense resistor.
Power ground return pin for low side MOSFET gate driver. Connect directly to the low side of the
channel2 current sense resistor.
Low side MOSFET gate drive output. Connect to the gate of the channel2 low-side synchronous
MOSFET through a short, low inductance path.
Bias supply pin. Locally decouple to PGND2 using a low ESR/ESL capacitor located as close to
controller as possible.
Switching node of the buck regulator. Connect to channel2 bootstrap capacitor, the source terminal
of the high-side MOSFET and the drain terminal of the low-side MOSFET.
High side MOSFET gate drive output. Connect to the gate of the channel2 high-side MOSFET
through a short, low inductance path.
High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel2 external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge
the high side MOSFET gate and should be placed as close to the controller as possible.
Under-voltage lockout programming pin. If the UVLO pin is below 0.4V, the regulator will be in the
shutdown mode with all function disabled. If the UVLO pin is greater than 0.4V and below 1.25V, the
regulator will be in standby mode with the VCC regulators operational, the SS pins grounded and no
switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25V, the SS pins are allowed
to ramp and pulse width modulated gate drive signals are delivered at the LO and HO pins. A 20µA
current source is enabled when UVLO exceeds 1.25V and flows through the external UVLO resistors
to provide hysteresis.
Supply voltage input source for the VCC regulators.
High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel1 external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge
the high side MOSFET gate and should be placed as close to controller as possible.
High side MOSFET gate drive output. Connect to the gate of the channel1 high-side MOSFET
through a short, low inductance path.
Switching node of the buck regulator. Connect to channel1 bootstrap capacitor, the source terminal
of the high-side MOSFET and the drain terminal of the low-side MOSFET.
Exposed pad of LLP package. No internal electrical connections. Solder to the ground plane to reduce
thermal resistance.
4