tmp86c809ng TOSHIBA Semiconductor CORPORATION, tmp86c809ng Datasheet
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... Bit Microcontroller TLCS-870/C Series TMP86C809NG ...
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... The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S © 2007 TOSHIBA CORPORATION Page 2 TMP86C809NG All Rights Reserved ...
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Date Revision 2006/10/19 1 2007/2/14 2 2007/2/14 3 2007/2/21 4 2007/2/28 5 Revision History First Release Periodical updating.No change in contents. Periodical updating.No change in contents. Contents Revised Contents Revised ...
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...
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... Table of Contents TMP86C809NG 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Memory Address Map............................................................................................................................... 7 2.1.2 Program Memory (MaskROM).................................................................................................................. 7 2.1.3 Data Memory (RAM) ................................................................................................................................. 7 2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 Clock Generator........................................................................................................................................ 8 2.2.2 Timing Generator .................................................................................................................................... 10 2.2.2.1 Configuration of timing generator 2.2.2.2 Machine cycle 2.2.3 Operation Mode Control Circuit .............................................................................................................. 11 2 ...
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Undefined Instruction Interrupt (INTUNDEF 3.7 Address Trap Interrupt (INTATRAP) . ...
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Programmable Pulse Generate (PPG) Output Mode ............................................................................. 77 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . ...
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SS pin ................................................................................................................................................. 115 11.5 SEI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). v ...
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vi ...
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... The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S CMOS 8-Bit Microcontroller TMP86C809NG RAM Package 512 P-SDIP32-400-1.78 bytes Page 1 TMP86C809NG FLASH MCU Emulation Chip TMP86F809NG TMP86C909/987XB 060116EBP ...
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... SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru- put.(CPU restarts). SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. interruput. 14. Wide operation voltage 16MHz /32.768 kHz 2 5 MHz /32.768 kHz Page 2 TMP86C809NG Release by ...
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... P12 ( DVO 9 24 (TXD) P00 P11 (INT1 (RXD) P01 P10 ( 11 22 INT0 (SCLK) P02 P07 (TC1/INT4 (MOSI) P03 P06 (INT3 (MISO) P04 P05 ( ) P14 P13 15 18 P16 P15 16 17 Figure 1-1 Pin Assignment Page 3 TMP86C809NG ) PDO4/PWM4/PPG4 ) PDO3/PWM3 ) ) ) PPG ...
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... Block Diagram 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86C809NG ...
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... PORT10 I External interrupt 0 input PORT22 IO Resonator connecting pins(32.768kHz) for inputting external O clock PORT21 IO Resonator connecting pins(32.768kHz) for inputting external I clock IO PORT20 I External interrupt 5 input I STOP mode release signal input IO PORT37 I Analog Input5 I STOP5 IO PORT36 I Analog Input4 I STOP4 Page 5 TMP86C809NG ...
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... Page 6 TMP86C809NG Functions PORT35 Analog Input3 STOP3 PORT34 Analog Input2 STOP2 PORT33 Analog Input1 PORT32 Analog Input0 PORT31 TC4 input PDO4/PWM4/PPG4 output PORT30 TC3 input PDO3/PWM3 output Resonator connecting pins for high-frequency clock ...
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... The TMP86C809NG has a 8192 bytes (Address E000H to FFFFH) of program memory (MaskROM ). 2.1.3 Data Memory (RAM) The TMP86C809NG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on ...
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... System Clock Controller Example :Clears RAM to “00H”. (TMP86C809NG) SRAMCLR: 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. XIN XOUT XTIN XTOUT 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware ...
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... The system to require the adjustment of the oscillation frequency should create the program for the adjust- ment in advance. Low-frequency clock XOUT XTIN XTOUT (Open) (c) Crystal Page 9 TMP86C809NG XTIN XTOUT (Open) (d) External oscillator ...
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... Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) ) pulses DVO Main system clock generator Multi- plexer Figure 2-4 Configuration of Timing Generator Page 10 TMP86C809NG Machine cycle counters Divider Multiplexer Warm-up controller ...
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... The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86C809NG is placed in this mode after reset ...
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... NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1 mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode. (3) SLOW1 mode This mode can be used to reduce power-consumption by turning off oscillation of the high-fre- quency clock. The CPU core and on-chip peripherals operate using the low-frequency clock. Page 12 TMP86C809NG ...
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... STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 13 TMP86C809NG pin. After STOP ...
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... Operate with low frequency Oscillation Halt Operate with low frequency Stop Halt Stop Page 14 TMP86C809NG RESET Reset release Note 2 SYSCR1<STOP> = "1" STOP pin input SYSCR2<XTEN> = "1" SYSCR1<STOP> = "1" STOP pin input SYSCR2<SYSCK> = "1" ...
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... CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) Page 15 TMP86C809NG (Initial value: 0000 00**) R/W R/W R/W R/W ...
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... Wait until the STOP F, SSTOPH ; IMF ← 0 (SYSCR1 Starts STOP mode Page 16 TMP86C809NG pin input and key-on wakeup input STOP (external interrupt input 5) pin. STOP mode is pin high or detecting high or low edge STOP pin input is high, STOP STOP is a falling edge-sensitive input). ...
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... STOP mode is not restarted. pin input is detected. STOP STOP ; IMF ← Starts after specified to the edge-sensitive release mode Page 17 TMP86C809NG NORMAL operation pin input. This is used in appli- pin. In STOP pin input is high level. STOP ...
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... STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 18 TMP86C809NG STOP operation NORMAL operation pin, which immediately RESET pin input voltage will ...
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... Figure 2-9 STOP Mode Start/Release Page 19 TMP86C809NG ...
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... Reset input No No Interrupt request Yes “0” IMF “1” (Interrupt release mode) Normal release mode Interrupt processing Execution of the instruc- tion which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 20 TMP86C809NG Yes Reset ...
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... IDLE1/2 and SLEEP1/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 21 TMP86C809NG pin. RESET ...
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... System Clock Controller Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 22 TMP86C809NG ...
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... Yes Reset input Reset No TBT No source clock falling edge Yes No TBTCR<TBTEN> = "1" Yes No TBT interrupt enable Yes No IMF = "1" Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Page 23 TMP86C809NG ...
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... IDLE0 and SLEEP0 modes can also be released by inputting low level on the nous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period set- ting by TBTCR<TBTCK>. started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be started. Page 24 TMP86C809NG pin. RESET ...
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... Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 25 TMP86C809NG ...
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... IMF 0 (EIRH Enables INTTC4 ← ; IMF 1 (TC4CR Starts TC4, 3 (TC4CR Stops TC4, 3 (SYSCR2 SYSCR2<SYSCK> (Switches the main system clock to the low-frequency clock) (SYSCR2 SYSCR2<XEN> (Turns off high-frequency oscillation) PINTTC4 ; INTTC4 vector table Page 26 TMP86C809NG ← 1 ← 0 ← 1 ← 1 ← 0 ...
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... Sets mode for TC4, 3 (16-bit mode, fc for source) ; Sets warming-up counter mode ; Sets warm-up time ← ; IMF 0 ; Enables INTTC4 ← ; IMF 1 ; Starts TC4 Stops TC4, 3 ← ; SYSCR2<SYSCK> 0 (Switches the main system clock to the high-frequency clock) ; INTTC4 vector table Page 27 TMP86C809NG ...
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... System Clock Controller Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 28 TMP86C809NG ...
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... Reset Circuit The TMP86C809NG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the sys- tem clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the max- imum 24/fc[s] ...
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... In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0” case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”. The reset time is maximum 24/fc (1.5 µs at 16.0 MHz). Address trap is occurred maximum 24/fc [s] 4/fc to 12/fc [s] Figure 2-16 Address Trap Reset Page 30 TMP86C809NG Reset release Instruction at address r 16/fc [s] ...
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... Page 31 TMP86C809NG ...
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... Reset Circuit Page 32 TMP86C809NG ...
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... Interrupt Control Circuit The TMP86C809NG has a total of 17 interrupt sources excluding reset, of which 1 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. ...
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... However, if using multiple interrupt on interrupt service routine, manipulat- ing should be executed before setting IMF="1". DI LDW (ILL), 1110100000111111B EI LD WA, (ILL) TEST (ILL SSET Page 34 TMP86C809NG ← ; IMF 0 ← ; IL12, IL10 to IL6 0 ← ; IMF 1 ← ← ...
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... Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); ← ; IMF 0 (EIRL), 1110100010100000B ; EF15 to EF13, EF11, EF7, EF5 Note: IMF should not be set. ← ; IMF 1 /* 3AH shows EIRL address */ Page 35 TMP86C809NG ← 1 ...
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... EF7 EF6 EF5 EF4 EIRL (003AH) 0: Disables the acceptance of each maskable interrupt. 1: Enables the acceptance of each maskable interrupt. 0: Disables the acceptance of all maskable interrupts 1: Enables the acceptance of all maskable interrupts TMP86C809NG R IMF R/W ...
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... The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved IL11ER - - - - 0: INTTC4 1: INT3 Page 37 TMP86C809NG (Initial value: ***0 ****) R/W ...
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... If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Interrupt acceptance − − 03H Vector D2H Page 38 TMP86C809NG Interrupt service task Execute Execute RETI instruction instruction − − Entry address Interrupt D203H ...
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... Save WA register WA ; Restore WA register ; RETURN PCL PCL PCH PCH PSW PSW At execution of POP instruction (GSAVA Save A register A, (GSAVA) ; Restore A register ; RETURN Interrupt Interrupt service task acceptance Saving registers Restoring registers Interrupt return Page 39 TMP86C809NG Address (Example) b-5 b-4 b-3 b-2 b execution of RETI instruction ...
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... Stack pointer (SP) is incremented by 3. POP WA ; Recover WA, Return Address ; PUSH WA ; Alter stacked data (interrupt processing) RETN ; RETURN INC SP ; Recover INC SP ; INC SP ; (interrupt processing) LD EIRL, data ; Set IMF to “1” or clear it to “0” JP Restart Address ; Jump into restarting address Page 40 TMP86C809NG ...
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... Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). 3.8 External Interrupts The TMP86C809NG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The rupt input pin or an input/output port, and is configured as an input port during reset ...
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... Falling and Rising edge or H level IMF EF15 = 1 Falling edge Page 42 TMP86C809NG Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are consid- ered to be signals ...
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... INT0 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: "H" level 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: "H" level 0: Rising edge 1: Falling edge Page 43 TMP86C809NG (Initial value: 0000 000*) R/W R/W R/W R/W R/W 6 /fc. pin is released. RESET pin is released. ...
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... External Interrupts Page 44 TMP86C809NG ...
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... Special Function Register (SFR) The TMP86C809NG adopts the memory mapped I/O system, and all peripheral control and data transfers are per- formed through the special function register (SFR). The SFR is mapped on address 0000H to 003FH. This chapter shows the arrangement of the special function register (SFR) for TMP86C809NG. ...
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... Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Read Write SESR - SEDR SECR Reserved Reserved Reserved Reserved Reserved Reserved - STOPCR Reserved Reserved - WDTCR1 - WDTCR2 TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH INTSEL PSW Page 46 TMP86C809NG ...
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... I/O Ports The TMP86C809NG have 4 parallel input/output ports as follows. Primary Function Port P0 8-bit I/O port Port P1 7-bit I/O port Port P2 3-bit I/O port Port P3 8-bit I/O port Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing ...
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... Figure 5-2 P0 Port P05 P04 P02 P03 MISO SCLK SS MOS P05 P04 P03 P02 0: Nch open-drain output 1: Push-pull output Page 48 TMP86C809NG P0i Note P01 P00 RxD TxD (Initial value: 1111 1111 P01 P00 R/W ...
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... Controls P1 port input/output P1CR (specified bitwise Output latch D Q Output latch Figure 5-3 P1 Port P14 P13 P12 P11 P10 INT1 DVO INT0 Input mode 1: Output mode Page 49 TMP86C809NG P1i Note (Initial value: ***0 0000) (Initial value: ***0 0000) R/W ...
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... Figure 5-4 P2 Port P22 XTOUT P22 pin, so that when in STOP mode, its output goes to a High-Z state regardless of the STOP Page 50 TMP86C809NG P20 (INT5 sc. enable P21 (XTIN) P22 (XT UT P21 P20 XTIN (Initial value: **** *111) INT5 STOP 1 0 ...
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... Data input (P3DR) Data output (P3DR) Control output Output latch Output latch a) Equivalent circuit of P32 to P37 Output latch Output latch b) Equivalent circuit of P30, P31 Figure 5-5 P3 Port Page 51 TMP86C809NG P3i Note Note Note 3: Functions enclosed with broken lines do not apply to P32 and P33 ...
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... AIN3 AIN2 AIN1 AIN0 TC4 STOP3 STOP2 PDO4 PWM4 PPG4 Input mode 1: Output mode Analog Input Mode Input Mode Page 52 TMP86C809NG 1 0 P30 TC3 (Initial value: 0000 0000) PDO3 PWM3 1 0 (Initial value: 0000 0000) Output Mode R/W ...
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... TBTEN TBTCK 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 23 000 fc/2 21 001 fc/2 16 010 fc/2 14 011 fc/2 13 100 fc/2 12 101 fc/2 11 110 fc/2 9 111 fc/2 Page 53 TMP86C809NG IDLE0, SLEEP0 release request INTTBT interrupt request 0 (Initial Value: 0000 0000) SLOW1/2 SLEEP1/2 DV7CK = 1 Mode 15 15 fs/2 fs fs/2 fs/2 8 – fs/2 R/W 6 – fs/2 5 – fs/2 4 – fs/2 3 – ...
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... NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 Interrupt period Enable TBT Figure 6-2 Time Base Timer Interrupt Page 54 TMP86C809NG ; TBTCK ← 010 ; TBTEN ← IMF ← 0 SLOW1/2, SLEEP1/2 Mode 128 – 512 – 1024 – 2048 – ...
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... Port output latch TBTCR<DVOEN> DVO pin output Figure 6-3 Divider Output (DV7CK) (TBTEN) (TBTCK) 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = fc/2 ) DVO fc/2 Page 55 TMP86C809NG (b) Timing chart 0 (Initial value: 0000 0000) R/W SLOW1/2 SLEEP1/2 DV7CK = 1 Mode 5 5 fs/2 fs/2 R fs/2 fs fs/2 fs fs/2 fs/2 ...
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... LD (TBTCR) , 10000000B Divider Output Frequency [Hz] NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 00 1.953 k 1.024 k 01 3.906 k 2.048 k 10 7.813 k 4.096 k 11 15.625 k 8.192 k Page 56 TMP86C809NG ; DVOCK ← "00" ; DVOEN ← "1" SLOW1/2, SLEEP1/2 Mode 1.024 k 2.048 k 4.096 k 8.192 k ...
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... S R WDTEN WDTT 0034 H WDTCR1 Watchdog timer control registers Figure 7-1 Watchdog Timer Configuration Binary counters Overflow WDT output Writing Writing disable code clear code Controller 0035 H WDTCR2 Page 57 TMP86C809NG Reset release R Reset S Q request Interrupt request INTWDT interrupt request WDTOUT ...
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... CPU malfunction detection (WDTCR2), 4EH : Clears the binary counters. ← (WDTCR1), 00001101B : WDTT 10, WDTOUT (WDTCR2), 4EH : Clears the binary counters (always clears immediately before and after changing WDTT). (WDTCR2), 4EH : Clears the binary counters. (WDTCR2), 4EH : Clears the binary counters. Page 58 TMP86C809NG ← 1 ...
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... Interrupt request 1: Reset request 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Page 59 TMP86C809NG 0 WDTOUT (Initial value: **11 1001) Write only SLOW1/2 mode 17 /fs 2 /fs ...
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... Clears the binary coutner ← (WDTCR1), 0B101H : WDTEN 0, WDTCR2 Watchdog Timer Detection Time[s] NORMAL1/2 mode DV7CK = 0 DV7CK = 1 2.097 4 524.288 m 1 131.072 m 250 m 32.768 m 62.5 m SP, 023FH : Sets the stack pointer ← (WDTCR1), 00001000B : WDTOUT 0 Page 60 TMP86C809NG ← Disable code SLOW mode 4 1 250 m 62.5 m ...
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... Clock 1 2 Binary counter Overflow INTWDT interrupt request (WDTCR1<WDTOUT>= "0") Internal reset (WDTCR1<WDTOUT>= "1") Write 4E Figure 7-2 Watchdog Timer Interrupt 19 2 / WDTCR2 H Page 61 TMP86C809NG (WDTT=11 reset occurs ...
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... D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Page 62 TMP86C809NG 1 0 (WDTOUT) (Initial value: **11 1001 (Initial value: **** ****) ...
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... Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura- cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 63 TMP86C809NG ...
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... Address Trap Page 64 TMP86C809NG ...
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... TimerCounter 1 (TC1) 8.1 Configuration Figure 8-1 TimerCounter 1 (TC1) Page 65 TMP86C809NG ...
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... Extrig- Win- Timer Event Pulse ger dow – – – – – – Divider DV7CK = 1 3 DV9 fs/2 7 DV5 fc/2 3 DV1 fc/2 External clock (TC1 pin input) TMP86C809NG R/W R/W PPG SLOW, SLEEP mode 3 fs/2 R/W – – R/W ...
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... Read the capture value in a capture enabled condition. Note 10:Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time. Page 67 TMP86C809NG ...
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... Enables INTTC1 ; IMF= “1” (TC1CR), 00000000B ; Selects the source clock and mode (TC1CR), 00010000B ; Starts TC1 ; ACAP1 ← 1 (TC1CR), 01010000B : WA, (TC1DRB) ; Reads the capture value Page 68 TMP86C809NG SLOW, SLEEP mode DV7CK = 1 Maximum Maximum Time Setting Resolution Time Set- [s] [µs] ting [s] 16.0 244.14 0.524 – ...
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... Counter m − 1 TC1DRB ? ACAP1 Figure 8-2 Timer Mode Timing Chart n − Match detect Counter clear (a) Timer mode Capture (b) Auto-capture Page 69 TMP86C809NG − Capture n − ...
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... Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 0 (TC1CR), 00100100B 7 (TC1DRA), 01F4H ; 4 ms ÷ 2 /fc = 1F4H ; IMF= “0” (EIRL Enables INTTC1 interrupt ; IMF= “1” (TC1CR), 00000100B ; Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 0 (TC1CR), 01110100B Page 70 TMP86C809NG ...
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... Match detect Count clear (a) Trigger start (METT1 = 0) Count clear Count start m − (b) Trigger start and stop (METT1 = 1) Page 71 TMP86C809NG At the rising edge (TC1S = 10) Count start the rising edge (TC1S = 10 Match detect Count clear Note: m < n ...
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... Table 8-2 Input Pulse Width to TC1 Pin Match detect Figure 8-4 Event Counter Mode Timing Chart Minimum Pulse Width [s] NORMAL1/2, IDLE1/2 Mode 3 High-going 2 /fc 3 Low-going 2 /fc Page 72 TMP86C809NG n − Counter clear SLOW1/2, SLEEP1/2 Mode /fs At the rising edge (TC1S = 10) ...
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... Figure 8-5 Window Mode Timing Chart Count stop Count start Match detect (a) Positive logic (TC1S = 10) Count stop (b) Negative logic (TC1S = 11) Page 73 TMP86C809NG Counter clear Count start Match detect Counter clear ...
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... Note 2: For the single-edge capture, the counter after capturing the value stops at “1” until detecting the next edge. Therefore, the second captured value is “1” larger than the captured value immediately after counting starts. Note 3: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value. Page 74 TMP86C809NG ...
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... INTTC1 interrupt, inverts and tests INTTC1 service switch F, SINTTC1 A, (TC1DRBL) ; Reads TC1DRB (High-level pulse width) W,(TC1DRBH) (HPULSE Stores high-level pulse width in RAM A, (TC1DRBL) ; Reads TC1DRB (Cycle) W,(TC1DRBH) (WIDTH Stores cycle in RAM ; Duty calculation PINTTC1 ; INTTC1 Interrupt vector WIDTH HPULSE Page 75 TMP86C809NG ...
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... Page 76 Count start Capture n [Application] High-or low-level pulse width measurement (MCAP1 = "1") Count start Capture n [Application] (1) Cycle/frequency measurement (2) Duty measurement (MCAP1 = "0") TMP86C809NG (TC1S = "10" (TC1S = "10" Capture m ...
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... Note 4: Set TC1DRB after changing the mode of TC1M to the PPG mode. pin retains the level immediately before PPG pin can be set with TC1CR<TFF1> when the timer starts, a positive or neg- pin, and “1” to set the low level to the PPG Page 77 TMP86C809NG pin, PPG pin. PPG ...
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... I/O port output latch shared with PPG output Q D Data output R Set Clear Q Toggle Timer F/F1 INTTC1 interrupt request TC1CR<TC1S> clear Figure 8-7 Output PPG Page 78 TMP86C809NG 7 / 007DH) 7 /fc = 0019H) 7 /fc µs = 007DH) 7 /fc = 0019H) Port output enable PPG pin Function output ...
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... TC1DRB m TC1DRA PPG pin output INTTC1 interrupt request (b) Figure 8-8 PPG Mode Timing Chart (a) Continuous pulse generation (TC1S = 01 [Application] One-shot pulse output One-shot pulse generation (TC1S = 10) Page 79 TMP86C809NG Note: m > n Note: m > n ...
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... Function Page 80 TMP86C809NG ...
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... B PWREG4 PWM, PPG mode 16-bit mode TC3S PWM mode Overflow PDO mode Timer, Event Couter mode PWM mode Figure 9-1 8-Bit TimerCouter 3, 4 Page 81 TMP86C809NG INTTC4 interrupt request Toggle Q Set PDO4/PWM4/ PPG4 pin Clear Timer F/F4 Decode EN PDO, PWM, PPG mode TFF4 INTTC3 ...
Page 92
... TC4M.) Reserved 1**: Page 82 TMP86C809NG 0 (Initial value: 1111 1111) 0 (Initial value: 1111 1111) 0 (Initial value: 0000 0000) SLOW1/2 SLEEP1/2 DV7CK = 1 ...
Page 93
... Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9- 3. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 83 TMP86C809NG ...
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... Reserved 16-bit timer/event counter mode 100: Warm-up counter mode 101: 16-bit pulse width modulation (PWM) output mode 110: 16-bit PPG mode 111: Page 84 TMP86C809NG 0 (Initial value: 1111 1111) 0 (Initial value: 1111 1111) 0 (Initial value: 0000 0000) SLOW1/2 SLEEP1/2 DV7CK = 1 mode ...
Page 95
... Page 85 TMP86C809NG TC3 TC4 fc pin input pin input – – – Ο Ο – – – – Ο – – – – ...
Page 96
... Warm-up counter 16-bit PWM 16-bit PPG Note Register Value 1≤ (TTREGn) ≤255 1≤ (TTREGn) ≤255 2≤ (PWREGn) ≤254 1≤ (TTREG4, 3) ≤65535 256≤ (TTREG4, 3) ≤65535 2≤ (PWREG4, 3) ≤65534 1≤ (PWREG4, 3) < (TTREG4, 3) ≤65535 and (PWREG4 < (TTREG4, 3) Page 86 TMP86C809NG ...
Page 97
... Hz and generating an interrupt 80 µs later (TTREG4), 0AH : Sets the timer register (80 µs (EIRH Enables INTTC4 interrupt. (TC4CR), 00010000B : Sets the operating cock to fc/2 (TC4CR), 00011000B : Starts TC4. Page 87 TMP86C809NG and pins may output pulses. PPGj Repeated Cycle MHz fs = 32.768 kHz 32.6 ms 62.3 ms 2.0 ms – ...
Page 98
... Counter clear Counter clear Match detect the NORMAL1/2 or IDLE1/2 mode, and fs/2 and pins may output PDOj, PWMj PPGj Counter Counter clear Match detect clear pin. PDOj pin is switched to the opposite state and PDOj TMP86C809NG ...
Page 99
... Sets the operating clock to fc/2 (TC4CR), 00011001B : Starts TC4. pin holds the output status when the timer is PDOj pin to the high level when the TimerCounter is stopped PDOj pin to the high level. PDOj Page 89 TMP86C809NG 2 = 3DH 7 , and 8-bit PDO mode. ...
Page 100
... Configuration Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) Page 90 TMP86C809NG ...
Page 101
... Page 91 TMP86C809NG Repeated Cycle MHz fs = 32.768 kHz 32.8 ms 62.5 ms 2.05 ms – 512 µs – 128 µs – 7. µs – 16 µs – ...
Page 102
... Configuration Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) Page 92 TMP86C809NG ...
Page 103
... Sets the 16-bit timer mode (upper byte). (TC4CR), 0CH : Starts the timer mn Match Counter detect clear Page 93 TMP86C809NG , and pins may output a pulse. PPGj Repeated Cycle MHz fs = 32.768 kHz 8. 524.3 ms – 131.1 ms – 32.8 ms – ÷ ...
Page 104
... Hz in the NORMAL1 or IDLE1 mode, and fs/2 4 pin is the opposite to the timer F/F4 logic level.) PWM 4 pin holds the output status when the timer is PWM 4 pin to the high level when the TimerCounter is stopped PWM Page 94 TMP86C809NG and pins may output pulses. PDOj, PWMj PPGj the SLOW1 ...
Page 105
... Sets the operating clock to fc/2 mode (lower byte). (TC4CR), 056H : Sets TFF4 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). (TC4CR), 05EH : Starts the timer. Page 95 TMP86C809NG 4 PWM Repeated Cycle MHz fs = 32.768 kHz 8. 524.3 ms – ...
Page 106
... Configuration Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 96 TMP86C809NG ...
Page 107
... PPG mode (upper byte). (TC4CR), 05FH : Starts the timer. 4 pin holds the output status when the timer is PPG 4 pin to the high level when the TimerCounter is stopped PPG 4 pin to the high level PPG Page 97 TMP86C809NG the SLOW1 and16-bit PPG mode ...
Page 108
... Configuration Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) Page 98 TMP86C809NG ...
Page 109
... IMF 1 (TC4CR).3 : Starts TC4 and 3. : (TC4CR).3 : Stops TC4 and 3. ← (SYSCR2).5 : SYSCR2<SYSCK> 1 (Switches the system clock to the low-frequency clock.) ← (SYSCR2).7 : SYSCR2<XEN> 0 (Stops the high-frequency clock.) : PINTTC4 : INTTC4 vector table Page 99 TMP86C809NG , and pins may output PDOi PWMi PPGi 1.99 s ...
Page 110
... Stops the TC4 and 3. CLR (SYSCR2).5 : SYSCR2<SYSCK> (Switches the system clock to the high-frequency clock.) CLR (SYSCR2).6 : SYSCR2<XTEN> (Stops the low-frequency clock.) RETI : : DW PINTTC4 : INTTC4 vector table Page 100 TMP86C809NG Maximum time (TTREG4 FF00H) 4.08 ms ← 1 ← 0 ← 1 ← 0 ← 0 ...
Page 111
... Baud rate generator Figure 10-1 UART (Asynchronous Serial Interface) Transmit data buffer TDBUF 2 Shift register Transmit/receive clock 2 Counter UARTSR UART status register UART control register 2 Page 101 TMP86C809NG Receive data buffer RDBUF Shift register Parity bit Stop bit Noise rejection RXD circuit TXD Y 6 ...
Page 112
... No noise rejection (Hysteresis input) 01: Rejects pulses shorter than 31/fc [s] as noise 10: Rejects pulses shorter than 63/fc [s] as noise 11: Rejects pulses shorter than 127/fc [s] as noise 0: 1 bit 1: 2 bits Page 102 TMP86C809NG 0 (Initial value: 0000 0000) 0 (Initial value: **** *000) Write only Write only ...
Page 113
... Receive data buffer full 0: On transmitting 1: Transmit end 0: Transmit data buffer full (Transmit data writing is finished) 1: Transmit data buffer empty Read only (Initial value: 0000 0000 Write only (Initial value: 0000 0000) Page 103 TMP86C809NG Read only ...
Page 114
... Start Bit 0 Bit 1 Start Bit 0 Bit 1 Start Bit 0 Bit 1 Start Bit 0 Bit 1 Figure 10-2 Transfer Data Format Without parity / 1 STOP bit With parity / 2 STOP bit Page 104 TMP86C809NG Bit 6 Bit 7 Stop 1 Bit 6 Bit 7 Stop 1 Stop 2 Bit 6 Bit 7 Parity Stop 1 Bit 6 ...
Page 115
... Start bit (a) Without noise rejection circuit Start bit Bit Start bit (b) With noise rejection circuit Page 105 TMP86C809NG 4 MHz 19200 [baud] 9600 4800 2400 1200 600 Bit ...
Page 116
... Note:When a receive operation is disabled by setting UARTCR1<RXE> bit to “0”, the setting becomes valid when data receive is completed. However framing error occurs in data receive, the receive-disabling setting may not become valid framing error occurs, be sure to perform a re-receive operation. Page 106 TMP86C809NG ...
Page 117
... The UARTSR<OERR> is cleared to “0” when the RDBUF is read after reading the UARTSR. Parity Stop xxxx0 ** pxxxx0 * Stop Final bit xxx0 ** xxxx0 * Page 107 TMP86C809NG 1pxxxx0 After reading UARTSR then RDBUF clears PERR. 0xxxx0 After reading UARTSR then RDBUF clears FERR. ...
Page 118
... UARTSR<TBEP> is set to “1”. The UARTSR<TBEP> is cleared to “0” when the TDBUF is written after reading the UARTSR. Final bit xxx0 ** xxxx0 yyyy Figure 10-7 Generation of Overrun Error Final bit xxxx0 xxx0 ** * yyyy Page 108 TMP86C809NG Stop 1xxxx0 * After reading UARTSR then RDBUF clears OERR. Stop 1xxxx0 xxxx After reading UARTSR then RDBUF clears RBFL. ...
Page 119
... Figure 10-10 Generation of Transmit End Flag and Transmit Data Buffer Empty Data write yyyy * 1xxxx **** 1x Bit 0 Final bit 1x ***** 1 **** Stop Data write for TDBUF Page 109 TMP86C809NG Data write zzzz ***** 1 1yyyy0 Stop After reading UARTSR writing TDBUF clears TBEP. * 1yyyy 1yyyy0 Bit 0 Start ...
Page 120
... Status Flag Page 110 TMP86C809NG ...
Page 121
... Serial Expansion Interface (SEI) SEI is one of the serial interfaces incorporated in the TMP86C809NG. It allows connection to peripheral devices via full-duplex synchronous communication protocols. The TMP86C809NG contain one channel of SEI. SEI is connected with an external device through SCLK, MOSI, MISO and the terminal and pins respectively are shared with P02, P03, P04 and P05. When using these ports as SCLK, MOSI, MISO pins, set the each Port Output Latch to “ ...
Page 122
... Clock phase mats”. 00: Divide-by-4 01: Divide-by-8 Selects SEI transfer rate 10: Divide-by-16 11: Divide-by-64 SER Internal Clock Divide Ratio of SEI Page 112 TMP86C809NG 1 0 SER (Initial value: 0000 0100) Transfer Rate when MHz 4 Mbps 2 Mbps 1 Mbps 250 kbps R/W ...
Page 123
... Transfer completed 0: No write collision error occurred #2 1: Write collision error occurred 0: No overflow occurred #3 1: Overflow occurred SED4 SED3 SED2 SED1 SED0 Page 113 TMP86C809NG = 4 2 (Initial value: 0000 ****) Read only R/W (Initial value: 0000 0000) ...
Page 124
... The programmable data and clock timing of SEI allows connection to almost all synchronous serial periph- eral devices. Refer to Section “" 11.5 SEI Transfer Formats "”. pin can be used to indicate multiple-master bus connection. SS CPHA SEI control register (SECR 002AH) bit 2 CPOL SEI control register (SECR 002AH) bit 3 Page 114 TMP86C809NG pin). For unselected slave devices, SS ...
Page 125
... SEI Pin Functions The TMP86C809NG have four input/output pins associated with SEI transfer. The functionality of each pin depends on the SEI device’s mode (master or slave). The SCLK pin, MOSI pin and MISO pin of all SEI devices are connected with the same name pin to each other . ...
Page 126
... Falling edge of transfer clock “H” level Rising edge of transfer clock pin goes “H” again before writing the next data to the SEDR register. SS Page 116 TMP86C809NG Data Sampling Rising edge of transfer clock Falling edge of transfer clock pin is “ ...
Page 127
... SEF flag is set before writing new data to the SEDR register Data Shift Data Sampling Rising edge of transfer clock Falling edge of transfer clock Falling edge of transfer clock Rising edge of transfer clock pin is “L” or “H”. Page 117 TMP86C809NG Internal shift clock ...
Page 128
... Master 8-bit shift register SEI clock MOSI MISO SCLK Figure 11-4 Master and Slave Connection in SEI Page 118 TMP86C809NG Slave MOSI 8-bit shift register MISO SCLK SS ...
Page 129
... Interrupt Generation The SEI for the TMP86C809NG uses INTSEI1. When the SESR<SEF> changes state from “0” to “1”, respective interrupts is generated. Table 11-6 SEI Interrupt SEI interrupt channel 1 (INTSEI1) 11.8 SEI System Errors The SEI has the facility to detect following two system errors. ...
Page 130
... When using the SEI pins as CMOS outputs, we recommend connecting them to the bus via resistors in order to protect the device against collision of drivers. However, be sure to select the appropriate resistance value which will not affect actual device operation (Example: 1 Ω to several kΩ). Page 120 TMP86C809NG ...
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... AD Converter (ADC) The TMP86C809NG have a 10-bit successive approximation type AD converter. 12.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 12-1. It consists of control register ADCCR1 and ADCCR2, converted value register ADCDR1 and ADCDR2 converter, a sample-hold circuit, a comparator, and a successive comparison circuit. ...
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... AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 0101: AIN5 0110: Reserved 0111: Reserved 1000: Reserved 1001: Reserved 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved 1111: Reserved Page 122 TMP86C809NG 1 0 SAIN (Initial value: 0001 0000) R/W ...
Page 133
... High Frequency oscillation clock [Hz AD06 AD05 AD04 AD03 AD02 ADBF Page 123 TMP86C809NG (Initial value: **0* 000*) R/W 5 MHz 2.5 MHz 15.6 µs - 15.6 µs 31.2 µs 31.2 µs 62.4 µs 62.4 µs 124.8 µs 124.8 µ (Initial value: 0000 0000) (Initial value: 0000 ****) ...
Page 134
... STOP mode or SLOW mode . Note read instruction is executed for ADCDR2, read data of bit3 to bit0 are unstable conversion end flag conversion BUSY flag 1: Page 124 TMP86C809NG Before or during conversion Conversion completed During stop of AD conversion During AD conversion Read only ...
Page 135
... ADCCR1<AMD> to “00” (Disable mode) by writing 0s. The AD convert operation is stopped immediately. The converted value at this time is not stored in the AD converted value register. AD conversion start 1st conversion result 2nd conversion result EOCF cleared by reading conversion result Conversion result Conversion result read read Conversion result Conversion result read read Page 125 TMP86C809NG ...
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... Conversion result read Conversion Conversion result read result read Figure 12-3 Repeat Mode Page 126 TMP86C809NG “00” AD convert operation suspended. Conversion result is not stored. 3rd conversion result EOCF cleared by reading conversion result Conversion Conversion result read ...
Page 137
... AD : converter registers. : (Refer to section I/O port in details) (ADCCR1) , 00100011B ; Select AIN3 ;Select conversion time(312/fc) and operation (ADCCR2) , 11011000B mode (ADCCR1 ADRS = 1(AD conversion start) (ADCDR2 EOCF SLOOP A , (ADCDR2) ; Read result data (9EH (ADCDR1) ; Read result data (9FH), A Page 127 TMP86C809NG ...
Page 138
... The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 12-4. 3FF H 3FE H 3FD H AD conversion result Figure 12-4 Analog Input Voltage and AD Conversion Result (Typ 1021 1022 1023 1024 Analog input voltage Page 128 TMP86C809NG VDD VSS 1024 ...
Page 139
... Toshiba also recommends attaching a capac- itor external to the chip. AINi Permissible signal source impedance 5 kΩ (max) Note Figure 12-5 Analog Input Equivalent Circuit and Example of Input Pin Processing Internal resistance Analog comparator 5 kΩ (typ) Internal capacitance (typ.) DA converter Page 129 TMP86C809NG ...
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... Precautions about AD Converter Page 130 TMP86C809NG ...
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... Key-on Wakeup (KWU) TMP86C809NG have four pins P34 to P37, in addition to the P20 ( mode. When using these P34 to P37 pin’s input to exit STOP mode, pay attention to the logic of P20 pin. In details, refer to the following section" 13.2 Control ". 13.1 Configuration STOP mode control ...
Page 142
... Edge detection mode: Rising edge Page 132 pin to release STOP mode. This is STOP pin is held low and STOP2 to STOP STOP 1 0 (Initial value : 0000 ****) 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable P3x Edge detection Rising or falling edge STOPCR: inhibited TMP86C809NG pin Write only ...
Page 143
... Input/Output Circuitry 14.1 Control Pins The input/output circuitries of the TMP86C809NG control pins are shown below. Control Pin I/O XIN Input XOUT Output Osc.enable XTIN Input XTOUT Input RESET Address trap reset Watchdog timer reset System clock reset TEST Input Note: The TEST pin of TMP86FH09/F809/F409NG does not have a pull-down resistor and diode(D1). Fix the TEST pin at Low level in MCU mode ...
Page 144
... Page 134 Sink open drain output VDD or Push-Pull output Hysteresis input High current output(Nch) R (Programmable port option) VDD Tri-state I/O Hysteresis input R VDD Sink open drain output Hysteresis input R VDD R P37 to 34 Tri-state I/O VDD Hysteresis input or CMOS input R P33,32 VDD R P31,30 TMP86C809NG Remarks ...
Page 145
... OUT1 I P1, P2, P3 ports OUT2 I P0 ports OUT3 Σ I P0, P1, P3 ports OUT1 Σ I P1, P2, P3 ports OUT2 Σ ports OUT3 P D Tsld Tstg Topr Page 135 TMP86C809NG (VSS = 0 V) Ratings Unit -0.3 to 6 -1 300 ...
Page 146
... V DD Hysteresis input V < 4 Except hysteresis input ≥ 4 Hysteresis input,TEST V < 4 2.7 to 5.5V DD XIN, XOUT V = 4 2.7 to 5.5V XTIN, XTOUT DD Page 136 TMP86C809NG ( Topr = -40 to 85°C) SS Min Max Unit 4.5 5.5 V 2.7 × 0. × 0. × 0. × 0. × 0.25 ...
Page 147
... 2.8 V/0 32.768 kHz 5.3 V/0 Condition AIN V = 3.0V/5 0 Page 137 TMP86C809NG = 0 V, Topr = - ° Min Typ. Max Unit – 0.9 – V µA – – ±2 – 70 – kΩ 100 220 450 – – ...
Page 148
... SLOW1, 2 modes SLEEP0 modes t WCH For external clock operation (XIN input MHz t WCL t WSH For external clock operation (XTIN input 32.768 kHz t WSL Page 138 TMP86C809NG = 0 V, 4.5 V ≤ V ≤ 5.5 V, Topr = -40 to 85° Min Typ. Max Unit 0.25 – 4 µs 117.6 – ...
Page 149
... The pass criteron of the above test is as follows: Solderability rate until forming ≥ When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend elec- trically shielding the package in order to maintain normal operating condition. XOUT XTOUT XTIN (2) Low-frequency Oscillation Page 139 TMP86C809NG ...
Page 150
... Handling Precaution Page 140 TMP86C809NG ...
Page 151
... Package Dimensions SDIP32-P-400-1.78 Rev 01 Page 141 TMP86C809NG Unit: mm ...
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... Page 142 TMP86C809NG ...
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This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). Toshiba provides a variety of development tools and basic software to enable efficient software development. These development tools have specifications ...
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