tc94a48fg TOSHIBA Semiconductor CORPORATION, tc94a48fg Datasheet - Page 19

• Manufacturer Part Number: tc94a48fg
• Description: Single-chip Audio Digital Signal Processor Single-chip Audio Digital Signal Processor
• Manufacturer: TOSHIBA Semiconductor CORPORATION

START
START I
SDA
SCL
I2C Address
2.2 I
2.2.1
Start Condition
2
(30h)
C Address W A
An interval of at least 1fs(32μs@1fs=32kHz)
(30h)
2
Figure 10 shows the data transfer format in I
In I
that the ACK bit is low. If the ACK bit is high, it retransmits a start condition (without transmitting a
stop condition) and then transfers an I
microcontroller transfers a 24-bit command. When the host microcontroller writes data to the
TC94A48FG, it writes as many 24-bit data words as specified with the 24-bit command (1 to 8 words)
and then transfers an end condition.
When the host microcontroller reads data from the TC94A48FG, it transfers a 24-bit command and
then, without transmitting an end condition, transfers an I
ACK bit is low. If the ACK bit is high, the host microcontroller retransmits a start condition (without
transmitting a stop condition) and then transfers an I
bit is low, the host microcontroller reads as many 24-bit data words as specified with the 24-bit
command (1 to 8 words). During a read, the host microcontroller sets the ACK bit to low after reading
every eight bits. The ACK bit accompanying the last eight bits must be set to high, after which the
host microcontroller transmits a stop condition. When transferring only a 24-bit command without
reading or writing data, transmit an end condition after transferring the command.
Figures 11 to 13 show the data transfer formats for writing, reading, and transferring a command
only.
C Bus Mode
W A
Data Transfer Format in I
is required before next START
I
2
C bus mode, the host microcontroller first transfers an I
2
C Address(30h)
COMMAND(H)
I
2
Each ACK signal sent from TC94A48FG to Host
C Address
START I
COMMAND(H)
Figure 13 Format for Transferring a Command Only
Figure 10 Data Transmission Format in I
A
24bit COMMAND
2
COMMAND(M)
C Address W A
Each ACK signal sent from TC94A48FG to Host
R/W ACK
(30h)
A
24bit COMMAND
COMMAND(M)
A
Figure 12 Format for Reading
Figure 11 Format for Writing
COMMAND(L)
DATA Hi(8bit)
An interval of at least 1fs(32μs@1fs=32kHz) is required before next START
2
C Bus Mode
A
COMMAND(H)
A
COMMAND(L)
2
Each ACK signal sent from
C address of 30h. After transferring an I
24bit Command and 24bit DATA (1～8word)
START
19
TC94A48FG to Host
A
ACK
2
These ACK signals are sent from host to TC94A48FG
A
C bus mode.
COMMAND(M)
I2C Address
24bit COMMAND
(31h)
DATA(H)
DATA Mid(8bit)
2
C address of 31h. After checking that the ACK
24bit Write DATA(1word 8word)
R A
A
A
2
C address (read =31h) and check that the
COMMAND(L)
2
This ACK signal is set to “H” by the Host
C address (write = 30h) and then checks
DATA(M)
RD(H)
24bit Read DATA(1word 8word)
2
C Mode
A
DATA Low(8bit)
A
RD(M)
A
STOP
～
A
DATA(L)
2
C address, the host
TC94A48FG
～
ACK
Stop Condition
2005-09-28
RD(L)
A
A
STOP
STOP