pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 235

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pxf4333

Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
7.2.13
Register 52 MASK0/MASK1
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
MASK0(15:0)
MASK1(15:0)
Data Sheet
15
7
Mask Registers
Table Access Mask Registers 0/1
14
Mask Register 0
Mask Register 1
Mask Registers 0..6 control the Write access from the respective
transfer registers to the internal tables on a per-bit selection basis.
The mask registers correspond to the respective transfer registers
(LCI0..LCI2,
MGT0..MGT2):
0
1
6
Read/Write
0000
MASK0
Written by CPU to control internal table Read/Write
access
H
13
5
The dedicated bit of the transfer register overwrites the
table entry during Write.
Does not affect Read access.
The dedicated bit of the transfer register does not
overwrite the table entry during Write.
Does not affect Read access.
55
TCT0..TCT3,
H
12
MASK(15:8)
4
MASK(7:0)
235
MASK1
11
3
QCT0..6,
10
2
56
Register Description
H
SBOC0..SBOC4,
PXF 4333 V1.1
9
1
2001-12-17
ABM-3G
8
0

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