pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 346

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Table 8-9
No.
80
81
82
83
84
85
86
87
Table 8-10
No.
80
81
82
83
In the following tables, AÞP (column DIR, Direction) defines a signal from the ATM
Layer (transmitter, driver) to the PHY Layer (receiver), A⇐P defines a signal from the
PHY Layer (transmitter, driver) to the ATM Layer (receiver).
Both UTOPIA Interfaces (PHY-side and Backplane-side) can be configured in either
Slave or Master Mode. If configured in Master Mode, the interface is considered to be
the ATM Layer device (A) and if configured in Slave Mode, the interface is considered to
be the PHY Layer device (P) respectively.
All timings also apply to UTOPIA Level 1 8-bit data bus operation.
•
•
Data Sheet
Signal Name DIR
UTXCLKD,
UTXCLKU
UTXDATD,
UTXDATU,
UTXPRTYD,
UTXPRTYU,
UTXSOCD,
UTXSOCU,
UTXENBD,
UTXENBU
UTXCLAVD,
UTXCLAVU
Signal Name DIR
URXCLKD,
URXCLKU
Transmit Timing (16-Bit Data Bus, 50 MHz Cell Mode, Single PHY)
Receive Timing (16-Bit Data Bus, 50 MHz Cell Mode, Single PHY)
A>P TxClk frequency (nominal)
A>P Input setup to TxClk
A<P Input setup to TxClk
A>P RxClk frequency (nominal)
Description
TxClk duty cycle
TxClk peak-to-peak jitter
TxClk rise/fall time
Input hold from TxClk
Input hold from TxClk
Description
URXCLKD:
URXCLKU:
RxClk duty cycle
RxClk peak-to-peak jitter
RxClk rise/fall time
346
Min
0
40
-
-
4
1
4
1
Min
0
0
40
-
-
Electrical Characteristics
Limit Values
Limit Values
PXF 4333 V1.1
Max
52
60
5
2
-
-
-
-
Max
52
52
60
5
2
2001-12-17
ABM-3G
Unit
MHz
%
%
ns
ns
ns
ns
ns
Unit
MHz
%
%
ns