pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 309

• Manufacturer Part Number: pxf4333
• Description: Abm 3g Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Register 108 WAR
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
WAR(15:0)
Data Sheet
15
7
Word Address Register
14
Word Address
This bit field selects an entry within the internal RAM/table selected
by the
In general, it can address up to 64K entries.
The current range of supported values depends on the size and
organization of the selected RAM/table.
Thus, the specific WAR register meaning is listed in the overview
part of each internal RAM/table description:
LCI
TCT
QCT
SBOC
QPTHU
QPTHD
QPTLU
QPTLD
6
Read/Write
0000
WAR
Written by CPU to address entries of internal RAM/
tables for Read or Write operation via transfer registers.
H
MAR
13
5
LCI Table RAM (see page 191)
Traffic Class Table (see page 195)
Queue Configuration Table (see page 223)
Scheduler Block Occupation Table (see page 223)
QPT High Word Upstream:
Queue Parameter Table (see page 247f.)
QPT High Word Downstream:
Queue Parameter Table (see page 247f.)
QPT Low Word Upstream:
Queue Parameter Table(see page 247)
QPT Low Word Downstream:
Queue Parameter Table (see page 247)
register.
EC
H
12
4
WAR(15:8)
WAR(7:0)
309
11
3
10
2
Register Description
PXF 4333 V1.1
9
1
2001-12-17
ABM-3G
8
0