atmega161-4pi ATMEL Corporation, atmega161-4pi Datasheet - Page 61

• Manufacturer Part Number: atmega161-4pi
• Description: 8-bit Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

EEPROM Control Register –
EECR
1228D–AVR–02/07
• Bits 7..4
These bits are reserved bits in the ATmega161 and will always read as zero.
• Bit 3
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is
enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt
generates a constant interrupt when EEWE is cleared (zero).
• Bit 2
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be
written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the
selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE
has been set (one) by software, hardware clears the bit to zero after four clock cycles.
See the description of the EEWE bit for an EEPROM write procedure.
• Bit 1
The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When
address and data are correctly set up, the EEWE bit must be set to write the value into
the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, oth-
erwise no EEPROM write takes place. The following procedure should be followed
when writing the EEPROM (the order of steps 2 and 3 is not essential):
1. Wait until EEWE becomes zero.
2. Write new EEPROM address to EEAR (optional).
3. Write new EEPROM data to EEDR (optional).
4. Write a logical “1” to the EEMWE bit in EECR (to be able to write a logical “1” to
5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.
Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the Global Interrupt Flag cleared during the four last steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared (zero) by hardware.
The user software can poll this bit and wait for a zero before writing the next byte. When
EEWE has been set, the CPU is halted for two cycles before the next instruction is
executed.
• Bit 0
The EEPROM Read Enable signal (EERE) is the read strobe to the EEPROM. When
the correct address is set up in the EEAR Register, the EERE bit must be set. When the
EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register.
The EEPROM read access takes one instruction and there is no need to poll the EERE
Bit
$1C ($3C)
Read/Write
Initial Value
the EEMWE bit, the EEWE bit must be written to zero in the same cycle).
–
–
–
–
EERIE: EEPROM Ready Interrupt Enable
EEMWE: EEPROM Master Write Enable
EEWE: EEPROM Write Enable
EERE: EEPROM Read Enable
–
Res: Reserved Bits
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
EERIE
R/W
3
0
EEMWE
R/W
2
0
ATmega161(L)
EEWE
R/W
X
1
EERE
R/W
0
0
EECR
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