p89lpc9402 NXP Semiconductors, p89lpc9402 Datasheet
p89lpc9402
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p89lpc9402 Summary of contents
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... V byte-erasable flash with 32 segment 4 LCD driver Rev. 01 — 22 April 2009 1. General description The P89LPC9402 is a multi-chip module consisting of a P89LPC931A1 single-chip microcontroller combined with a PCF8576D universal LCD driver in a low-cost 64-pin package. The LCD driver provides 32 segments and supports from backplanes. ...
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... I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. I Only power and ground connections are required to operate the P89LPC9402 when internal reset option is selected. I Four interrupt priority levels. I Eight keypad interrupt inputs, plus two additional external interrupt inputs ...
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... Package Name Description LQFP64 plastic low profile quad flat package; 64 leads; body 14 Part options Flash memory 8 kB Rev. 01 — 22 April 2009 P89LPC9402 14 1.4 mm Temperature range +85 C © NXP B.V. 2009. All rights reserved. Version SOT791-1 Frequency 0 MHz to 18 MHz ...
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... NXP Semiconductors 4. Block diagram P3[1:0] P2.5, P2[3:0] P1[7:0] P0[7:0] Fig 1. Block diagram P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core P89LPC931A1 MCU Rev. 01 — 22 April 2009 P89LPC9402 S[31:0] BP[3:0] PCF8576D LCD CONTROLLER V LCD 002aae470 © NXP B.V. 2009. All rights reserved ...
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... PORT 0 CONFIGURABLE I/Os KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE CPU OSCILLATOR DIVIDER clock ON-CHIP RC CONFIGURABLE OSCILLATOR OSCILLATOR WITH CLOCK DOUBLER Rev. 01 — 22 April 2009 P89LPC9402 TXD UART RXD SCL 2 I C-BUS SDA SPICLK MOSI SPI MISO REAL-TIME CLOCK/ SYSTEM TIMER T0 TIMER 0 ...
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... CIN2B KBI2 CIN2A KBI3 CIN1B PORT 0 KBI4 CIN1A KBI5 CMPREF KBI6 CMP1 KBI7 T1 XTAL2 PORT 3 XTAL1 P89LPC9402 functional diagram Rev. 01 — 22 April 2009 P89LPC9402 S[31:0] DISPLAY SEGMENT OUTPUTS DISPLAY LATCH SHIFT REGISTER INPUT DISPLAY BANK RAM SELECTOR 40 4 BITS SELECTOR DATA POINTER ...
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... Port 0 also provides various special functions as described below: P0.0 — Port 0 bit 0. CMP2 — Comparator 2 output KBI0 — Keyboard input 0. Rev. 01 — 22 April 2009 P89LPC9402 P89LPC9402 002aae473 Section 7.14.1 “Port for details. © NXP B.V. 2009. All rights reserved. S17 ...
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... P1.3 — Port 1 bit 3 (open-drain when used as output). INT0 — External interrupt 0 input. 2 SDA — I C-bus serial data input/output. P1.4 — Port 1 bit 4. High current source. INT1 — External interrupt 1 input. Rev. 01 — 22 April 2009 P89LPC9402 Section 7.14.1 “Port for details. P1.2 to P1.3 © NXP B.V. 2009. All rights reserved ...
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... C-bus data signal for the LCD controller. 2 SCL LCD — I C-bus clock signal for the LCD controller. BP0 to BP3: LCD backplane outputs. Rev. 01 — 22 April 2009 P89LPC9402 Section 7.14.1 “Port for details. Section 7.14.1 “Port for details. © NXP B.V. 2009. All rights reserved. ...
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... S0 to S31: LCD segment outputs. Ground reference. Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. LCD power supply: LCD voltage. Rev. 01 — 22 April 2009 P89LPC9402 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC9402 User manual for a more detailed functional description. 7.1 Special function registers Remark: Special Function Registers (SFRs) accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. ...
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Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H AUXR1 Auxiliary function register A2H Bit address B* B register F0H [1] BRGR0 Baud rate generator rate low BEH ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. I2SCLH Serial clock generator/SCL DDH duty cycle register high I2SCLL Serial clock generator/SCL DCH duty cycle register low 2 I2STAT I C-bus status ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. P0M1 Port 0 output mode 1 84H P0M2 Port 0 output mode 2 85H P1M1 Port 1 output mode 1 91H P1M2 Port ...
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... BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC9402 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000. ...
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Table 5. Extended special function registers Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register RTCDATH Real-time clock FFBFH data register high RTCDATL Real-time clock FFBEH data register low [1] ...
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... NXP Semiconductors 7.2 Enhanced CPU The P89LPC9402 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC9402 device has several internal clocks as defined below: OSCCLK — ...
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... Idle mode, it may be turned off prior to entering Idle, saving additional power. 7.4 On-chip RC oscillator option The P89LPC9402 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies ...
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... MEDIUM FREQUENCY XTAL2 LOW FREQUENCY RC OSCILLATOR WITH CLOCK DOUBLER (7.3728 MHz/14.7456 MHz WATCHDOG OSCILLATOR (400 kHz Fig 6. Block diagram of oscillator control - P89LPC9402 P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core OSCCLK RCCLK TIMER 0 AND TIMER 1 Rev. 01 — 22 April 2009 ...
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... Low power select The P89LPC9402 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access ...
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... LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request external interrupt is enabled when the P89LPC9402 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.16 “Power reduction modes” ...
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... Interrupt sources, interrupt enables, and power-down wake-up sources 7.14 I/O ports The P89LPC9402 has four I/O ports: Port 0 and Port 1 are 8-bit ports. Port 5-bit port. Port 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 7 ...
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... NXP Semiconductors 7.14.1 Port configurations All but three I/O port pins on the P89LPC9402 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open-drain, and input-only. Two configuration registers for each port select the output type for each port pin. 1. P1.5 (RST) can only be an input and cannot be confi ...
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... Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only or open-drain. Every output on the P89LPC9402 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to specifi ...
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... The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software. 7.16 Power reduction modes The P89LPC9402 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode. 7.16.1 Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated ...
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... For any other reset, previously set flag bits that have not been cleared will remain set. 7.17.1 Reset vector Following reset, the P89LPC9402 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address = 00H ...
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... RTC/system timer The P89LPC9402 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake- interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF fl ...
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... Section 7.20.5 “Baud rate generator and 7.20.5 Baud rate generator and selection The P89LPC9402 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate ...
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... If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core bit (bit 8) in double buffering (modes 1, 2 and 3) Rev. 01 — 22 April 2009 P89LPC9402 © NXP B.V. 2009. All rights reserved ...
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... C-bus interface that supports data transfers up to 400 kHz C-bus P1.3/SDA P1.2/SCL P89LPC9402 2 I C-bus configuration Rev. 01 — 22 April 2009 P89LPC9402 Figure 9. The P89LPC9402 device provides OTHER DEVICE OTHER DEVICE 2 2 WITH I C-BUS WITH I C-BUS INTERFACE INTERFACE 002aae474 © ...
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... STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram Rev. 01 — 22 April 2009 P89LPC9402 8 I2ADR ADDRESS REGISTER COMPARATOR SHIFT REGISTER ACK I2DAT 8 BIT COUNTER / ARBITRATION TIMING AND SYNC LOGIC AND CONTROL LOGIC ...
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... NXP Semiconductors 7.22 SPI The P89LPC9402 provides another high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode 4.5 Mbit/s can be supported in Master mode Mbit/s in Slave mode. It has a transfer completion flag and write collision fl ...
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... MOSI REGISTER SPICLK SPI CLOCK SS/PORT GENERATOR master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK SS/PORT GENERATOR Rev. 01 — 22 April 2009 P89LPC9402 slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK SS/PORT 002aab467 slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK ...
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... Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK port GENERATOR port Rev. 01 — 22 April 2009 P89LPC9402 slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK SS slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK ...
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... NXP Semiconductors 7.23 Analog comparators Two analog comparators are provided on the P89LPC9402. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage) ...
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... In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs. P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Rev. 01 — 22 April 2009 P89LPC9402 © NXP B.V. 2009. All rights reserved ...
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... Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few few seconds. Please refer to the P89LPC9402 User manual for more details. MOV WFEED1, #0A5H MOV WFEED2, #05AH ...
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... NXP Semiconductors 7.27 LCD driver 7.27.1 General description The LCD segment driver in the P89LPC9402 can interface to most LCDs using low multiplex rates. It generates the drive signals for static or multiplexed LCDs containing up to four backplanes and segments. The LCD controller communicates to a host using the I LCD driver are available on the P89LPC9402 providing system fl ...
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... P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core /24. osc(LCD) 4-bit RAM which stores LCD data. There is a one-to-one Rev. 01 — 22 April 2009 P89LPC9402 © NXP B.V. 2009. All rights reserved ...
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... C-bus slave receiver. In the P89LPC9402 the hardware Rev. 01 — 22 April 2009 P89LPC9402 Table 9. Blinking off 0 1536 Hz at pin CLK. The oscillator setting the hardware subaddress = 0. SS © NXP B.V. 2009. All rights reserved. ...
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... Flash organization The program memory consists of eight 1 kB sectors on the P89LPC9402 device. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time ...
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... P89LPC9402 through the serial port. This firmware is provided by NXP and embedded within each P89LPC9402 device. The NXP ISP facility has made ISP in an embedded application possible with a minimum of additional expense ...
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... Power-on reset code execution The P89LPC9402 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89LPC9402 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’ ...
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... Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted. P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core [1] Conditions except V , with respect transfer, not device power consumption Rev. 01 — 22 April 2009 P89LPC9402 Min Max Unit 55 +125 C 65 +150 ...
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... V SS except XTAL1, XTAL2 with respect [ th(HL) [8] all ports 1 3 Rev. 01 — 22 April 2009 P89LPC9402 [1] Min Typ Max - 3 1 0.22V ...
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... Conditions 2.4 V < V < 3.6 V; with DD BOV = 1, BOPD = 0 specifications are measured using an external clock with the following functions disabled: comparators, for steady state (non-transient) limits on I Rev. 01 — 22 April 2009 P89LPC9402 [1] Min Typ Max 2.40 - 2.70 1.11 1.23 1 ...
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... Figure 17 - see Figure 17 - see Figure 17 150 0 - see Figure 19, 20, 21 CCLK 4 CCLK see Figure 21, 22 250 Rev. 01 — 22 April 2009 P89LPC9402 MHz Unit osc Max Min Max 7.557 7.189 7.557 MHz 520 320 520 ...
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... Figure 21 see Figure 21 see Figure 19, 20, 21 see Figure 19, 0 20, 21, 22 see Figure 19, 20, 21 see Figure 19, 20, 21 Rev. 01 — 22 April 2009 P89LPC9402 MHz Unit osc Max Min Max - 250 - ns - 165 - ns - 250 - ns - 165 - ns - 250 - ns - 100 - ns - 100 - ns 120 0 ...
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... Figure 17 - see Figure 17 - see Figure 17 150 0 - see Figure 19, 20, 21 CCLK 4 CCLK see Figure 21, 22 250 see Figure 21, 22 250 Rev. 01 — 22 April 2009 P89LPC9402 MHz osc Max Min Max 7.557 7.189 7.557 MHz 520 320 520 125 - 15 - ...
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... Figure 21 see Figure 19, 20, 21 see Figure 19, 0 20, 21, 22 see Figure 19, 20, 21 see Figure 19, 20, 21 Rev. 01 — 22 April 2009 P89LPC9402 MHz Unit osc Max Min Max - 111 - ns - 167 - ns - 111 - ns - 167 - ns - 100 - ns - 100 - 160 ...
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... SPICLKL t SPICLKH t t SPIF SPIR t SPICLKL t SPICLKH t t SPIDSU SPIDH MSB/LSB SPIDV SPIOH master MSB/LSB out Rev. 01 — 22 April 2009 P89LPC9402 valid valid valid t CHCX t CLCH T cy(clk) 002aaa907 = 200 mV) t SPIR LSB/MSB in t SPIDV master LSB/MSB out 002aaa908 7 set TI ...
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... SPIR t SPICLKL t SPICLKH t t SPIOH SPIOH t t SPIDV SPIDV slave MSB/LSB out t t SPIDH SPIDSU MSB/LSB in Rev. 01 — 22 April 2009 P89LPC9402 t SPIR LSB/MSB SPIDV SPIDV t SPIR master LSB/MSB out 002aaa909 t SPIR t SPILAG t t SPIOH SPIDIS slave LSB/MSB out not defined ...
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... SPICLKH t t SPIOH SPIOH t t SPIDV SPIDV slave MSB/LSB out SPIDSU SPIDH SPIDSU MSB/LSB in Conditions Rev. 01 — 22 April 2009 P89LPC9402 t SPIR t SPILAG t SPIDIS slave LSB/MSB out t t SPIDSU SPIDH LSB/MSB in 002aaa911 Min Typ Max 002aaa912 © ...
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... LI [1] This parameter is characterized, but not tested in production. P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Conditions Min - 0 [ < V < Rev. 01 — 22 April 2009 P89LPC9402 Typ Max Unit - 0 250 500 ...
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... scale (1) ( 0.45 0.20 14.1 14.1 16.15 16.15 0.8 0.30 0.09 13.9 13.9 15.85 15.85 REFERENCES JEDEC JEITA MS-026 ED-7311EC Rev. 01 — 22 April 2009 P89LPC9402 detail 0.75 1.2 1 0.2 0.2 0.1 0.45 0.8 EUROPEAN PROJECTION SOT791 ( 0.8 ...
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... Erasable Programmable Read-Only Memory Electro-Magnetic Interference Liquid Crystal Display Light Emitting Diode Pulse Width Modulator Random Access Memory Resistance-Capacitance Real-Time Clock Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter WatchDog Timer Rev. 01 — 22 April 2009 P89LPC9402 © NXP B.V. 2009. All rights reserved ...
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... Revision history Document ID Release date P89LPC9402_1 20090422 P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Data sheet status Change notice Product data sheet - Rev. 01 — 22 April 2009 P89LPC9402 Doc. number Supersedes - - © NXP B.V. 2009. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 22 April 2009 P89LPC9402 © NXP B.V. 2009. All rights reserved ...
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... Software reset . . . . . . . . . . . . . . . . . . . . . . . . 37 7.26.2 Dual data pointers . . . . . . . . . . . . . . . . . . . . . 37 7.27 LCD driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.27.1 General description . . . . . . . . . . . . . . . . . . . . 38 7.27.2 Functional description . . . . . . . . . . . . . . . . . . 38 7.27.3 LCD bias voltages . . . . . . . . . . . . . . . . . . . . . 38 7.27.4 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.27.4.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.27.5 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.27.6 Display register 7.27.7 Segment outputs . . . . . . . . . . . . . . . . . . . . . . 39 7.27.8 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 39 7.27.9 Display RAM 7.27.10 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Rev. 01 — 22 April 2009 P89LPC9402 continued >> © NXP B.V. 2009. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com P89LPC9402 All rights reserved. Date of release: 22 April 2009 Document identifier: P89LPC9402_1 ...