lpc1765 NXP Semiconductors, lpc1765 Datasheet
lpc1765
Available stocks
Related parts for lpc1765
lpc1765 Summary of contents
Page 1
LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 02 — 11 February 2009 1. General description The LPC1768/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring ...
Page 2
... NXP Semiconductors I Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers. I Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1768/66/64 only), and the USB interface ...
Page 3
... NXP Semiconductors N System tick timer, including an external clock input option. N Repetitive interrupt timer provides programmable and repeating timed interrupts. N Each peripheral has its own clock divider for further power savings. I Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options ...
Page 4
... Ordering options Table 2. Ordering options Type number Flash LPC1768FBD100 512 kB LPC1766FBD100 256 kB LPC1765FBD100 256 kB LPC1764FBD100 128 kB LPC1768_66_65_64_2 Objective data sheet Description plastic low profile quad flat package; 100 leads; body 14 plastic low profile quad flat package; 100 leads; body 14 plastic low profi ...
Page 5
... NXP Semiconductors 5. Block diagram debug JTAG port interface TEST/DEBUG INTERFACE ARM CORTEX-M3 I-code D-code bus bus P0 to HIGH-SPEED P4 GPIO APB slave group 0 SCK1 SSEL1 SSP1 MISO1 MOSI1 RXD0/TXD0 UART0/1 8 UART1 RD1/2 CAN1/2 TD1/2 SCL0/1 I2C0/1 SDA0/1 SCK/SSEL SPI0 MOSI/MISO 2 MAT0/1 TIMER 0/1 ...
Page 6
... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD3/ 46 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 47 I/O SCL1 O I I/O [2] P0[2]/TXD0/AD0[ [2] P0[3]/RXD0/AD0[ [1] P0[4]/ 81 I/O I2SRX_CLK/ I/O RD2/CAP2[ LPC1768_66_65_64_2 Objective data sheet 1 LPC176xFBD100 25 Pin configuration LQFP100 package Description Port 0: Port 32-bit I/O port with individual direction controls for each bit ...
Page 7
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[5]/ 80 I/O I2SRX_WS/ I/O TD2/CAP2[ [1] P0[6]/ 79 I/O I2SRX_SDA/ I/O SSEL1/MAT2[0] I/O O [1] P0[7]/ 78 I/O I2STX_CLK/ I/O SCK1/MAT2[1] I/O O [1] P0[8]/ 77 I/O I2STX_WS/ I/O MISO1/MAT2[2] I/O O [1] P0[9]/ 76 I/O I2STX_SDA/ I/O MOSI1/MAT2[3] I/O O [1] P0[10]/TXD2/ 48 I/O SDA2/MAT3[0] O I/O O [1] P0[11]/RXD2/ 49 I/O SCL2/MAT3[1] I I/O O [1] P0[15]/TXD1/ 62 I/O SCK0/SCK O I/O I/O LPC1768_66_65_64_2 Objective data sheet Description P0[5] — General purpose digital input/output pin. ...
Page 8
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[16]/RXD1/ 63 I/O SSEL0/SSEL I I/O I/O [1] P0[17]/CTS1/ 61 I/O MISO0/MISO I I/O I/O [1] P0[18]/DCD1/ 60 I/O MOSI0/MOSI I I/O I/O [1] P0[19]/DSR1/ 59 I/O SDA1 I I/O [1] P0[20]/DTR1/SCL1 58 I/O O I/O [1] P0[21]/RI1/RD1 57 I [1] P0[22]/RTS1/TD1 56 I [2] P0[23]/AD0[0]/ 9 I/O I2SRX_CLK/ I CAP3[0] I/O I [2] P0[24]/AD0[1]/ 8 I/O I2SRX_WS/ I CAP3[1] I/O I [2] P0[25]/AD0[2]/ 7 I/O I2SRX_SDA/ I TXD3 I/O O LPC1768_66_65_64_2 ...
Page 9
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [3] P0[26]/AD0[3]/ 6 I/O AOUT/RXD3 [4] P0[27]/SDA0/ 25 I/O USB_SDA I/O I/O [4] P0[28]/SCL0/ 24 I/O USB_SCL I/O I/O [5] P0[29]/USB_D+ 29 I/O I/O [5] P0[30]/USB_D 30 I/O I/O P1[0] to P1[31] I/O [1] P1[0]/ 95 I/O ENET_TXD0 O [1] P1[1]/ 94 I/O ENET_TXD1 O [1] P1[4]/ 93 I/O ENET_TX_EN O [1] P1[8]/ 92 I/O ENET_CRS I [1] P1[9]/ 91 I/O ENET_RXD0 I [1] P1[10]/ 90 I/O ENET_RXD1 I [1] P1[14]/ 89 I/O ENET_RX_ER I [1] P1[15]/ 88 I/O ENET_REF_CLK I [1] P1[16]/ 87 I/O ENET_MDC O [1] P1[17]/ 86 I/O ENET_MDIO ...
Page 10
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[18]/ 32 I/O USB_UP_LED/ O PWM1[1]/ CAP1[ [1] P1[19]/MC0A/ 33 I/O USB_PPWR O CAP1[ [1] P1[20]/MCFB0/ 34 I/O PWM1[2]/SCK0 I O I/O [1] P1[21]/MCABORT/ 35 I/O PWM1[3]/ O SSEL0 O I/O [1] P1[22]/MC0B/ 36 I/O USB_PWRD/ O MAT1[ [1] P1[23]/MCFB1/ 37 I/O PWM1[4]/MISO0 I O I/O [1] P1[24]/MCFB2/ 38 I/O PWM1[5]/MOSI0 I O I/O [1] P1[25]/MC1A/ 39 I/O MAT1[ [1] ...
Page 11
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[27]/CLKOUT 43 I/O /USB_OVRCR/ O CAP0[ [1] P1[28]/MC2A 44 I/O 1[0]/ O MAT0[ [1] P1[29]/MC2B/ 45 I/O PCAP1[1]/ O MAT0[ [2] P1[30]/ I/O BUS AD0[ [2] P1[31]/SCK1/ 20 I/O AD0[5] I/O I P2[0] to P2[31] I/O [1] P2[0]/PWM1[1]/ 75 I/O TXD1 O O [1] P2[1]/PWM1[2]/ 74 I/O RXD1 O I [1] P2[2]/PWM1[3]/ 73 I/O CTS1/ O TRACEDATA[ [1] P2[3]/PWM1[4]/ 70 I/O DCD1/ O TRACEDATA[2] ...
Page 12
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P2[5]/PWM1[6]/ 68 I/O DTR1/ O TRACEDATA[ [1] P2[6]/PCAP1[0]/ 67 I/O RI1/TRACECLK [1] P2[7]/RD2/ 66 I/O RTS1 I O [1] P2[8]/TD2/ 65 I/O TXD2 O O [1] P2[9]/ 64 I/O USB_CONNECT/ O RXD2 I [6] P2[10]/EINT0/NMI 53 I [6] P2[11]/EINT1/ 52 I/O I2STX_CLK I I/O [6] P2[12]/EINT2/ 51 I/O I2STX_WS I I/O [6] P2[13]/EINT3/ 50 I/O I2STX_SDA I I/O P3[0] to P3[31] I/O [1] P3[25]/MAT0[0]/ 27 I/O PWM1[2] ...
Page 13
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P3[26]/STCLK/ 26 I/O MAT0[1]/PWM1[ P4[0] to P4[31] I/O [1] P4[28]/RX_MCLK/ 82 I/O MAT2[0]/TXD3 [1] P4[29]/TX_MCLK/ 85 I/O MAT2[1]/RXD3 [1] TDO/SWO [1] TDI 2 I [1] TMS/SWDIO 3 I I/O [1] TRST 4 I [1] TCK/SWDCLK [1] RTCK 100 I/O RSTOUT 14 O [7] RESET ...
Page 14
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [ DDA [8] VREFP 12 I VREFN 15 I [8] VBAT tolerant pad providing digital I/O functions with TTL levels and hysteresis. [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled ...
Page 15
... NXP Semiconductors Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on offi ...
Page 16
APB1 peripherals 0x4010 0000 31 system control 0x400F C000 not used 0x400C 0000 QEI 15 0x400B C000 14 motor control PWM 0x400B 8000 not used 13 0x400B 4000 repetitive interrupt timer 12 0x400B 0000 not used 11 ...
Page 17
... NXP Semiconductors 7.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.7.1 Features • Controls system exceptions and peripheral interrupts • In the LPC1768/66/65/64, the NVIC supports 33 vectored interrupts • ...
Page 18
... NXP Semiconductors 7.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • ...
Page 19
... GPIO pin. 7.11 Ethernet (LPC1768/66/64 only) Remark: The Ethernet controller is not available for part LPC1765. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, fl ...
Page 20
... NXP Semiconductors • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. ...
Page 21
... NXP Semiconductors • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC1768/66/65/64 can enter one of the reduced power modes and wake up on USB activity. ...
Page 22
... NXP Semiconductors 7.13.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1 . • Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. ...
Page 23
... NXP Semiconductors 7.16 UARTs The LPC1768/66/65/64 each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. ...
Page 24
... NXP Semiconductors 7.18.1 Features • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • DMA transfers supported by GPDMA 2 7 ...
Page 25
... NXP Semiconductors 2 The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I always the master, and one slave. The I separate transmit and receive channel, each of which can operate as either a master or a slave ...
Page 26
... NXP Semiconductors – Toggle on match. – Do nothing on match. • two match registers can be used to generate timed DMA requests. 7.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC1768/66/65/64. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specifi ...
Page 27
... NXP Semiconductors • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • ...
Page 28
... NXP Semiconductors 7.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals ...
Page 29
... NXP Semiconductors 7.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC1768/66/65/64 is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up ...
Page 30
... NXP Semiconductors LPC17xx MAIN OSCILLATOR INTERNAL RC OSCILLATOR 32 kHz RTC OSCILLATOR Fig 4. LPC1768/66/65/64 clocking generation block diagram 7.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range ...
Page 31
... NXP Semiconductors 7.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘ ...
Page 32
... NXP Semiconductors whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution ...
Page 33
... NXP Semiconductors The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up ...
Page 34
... NXP Semiconductors 7.29.8 Power domains The LPC1768/66/65/64 provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC1768/66/65/64, I/O pads are powered by the 3 DD(REG)(3V3) CPU and most of the peripherals. ...
Page 35
... NXP Semiconductors Fig 5. 7.30 System control 7.30.1 Reset Reset has four sources on the LPC1768/66/65/64: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating ...
Page 36
... NXP Semiconductors 7.30.2 Brownout detection The LPC1768/66/65/64 include 2-stage monitoring of the voltage on the V pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register ...
Page 37
... NXP Semiconductors 7.30.5 AHB multilayer matrix The LPC1768/66/65/64 use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32KB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories ...
Page 38
... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg P total power dissipation (per package) tot(pack) V electrostatic discharge voltage esd [1] The following applies to the limiting values: a) This product includes circuitry specifi ...
Page 39
... NXP Semiconductors Table 5. Thermal characteristics +85 C; unless otherwise specified. DD amb Symbol Parameter R thermal resistance from th(j-a) junction to ambient T maximum junction j(max) temperature LPC1768_66_65_64_2 Objective data sheet Conditions LQFP100 package Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller ...
Page 40
... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics +85 C unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V regulator supply voltage DD(REG)(3V3) (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin i(VREFP) VREFP ...
Page 41
... NXP Semiconductors Table 6. Static characteristics +85 C unless otherwise specified. amb Symbol Parameter I regulator supply current DD(REG)(3V3) (3 active mode battery BATact supply current 2 I C-bus pins (P0[27] and P0[28]) V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys ...
Page 42
... NXP Semiconductors Table 6. Static characteristics +85 C unless otherwise specified. amb Symbol Parameter USB pins I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold voltage V LOW-level output OL voltage for ...
Page 43
... NXP Semiconductors 10.1 Power consumption (X) Fig 6. (X) Fig 7. LPC1768_66_65_64_2 Objective data sheet <tbd> Conditions active mode entered executing code from flash; core voltage 2.7 V; all amb peripherals enabled but not configured to run. Regulator supply current at different core frequencies in active mode ...
Page 44
... NXP Semiconductors (X) Fig 8. (X) Fig 9. Table 7. Core voltage 3 Peripheral Timer0 Timer1 Timer2 Timer3 LPC1768_66_65_64_2 Objective data sheet <tbd> Conditions: active mode entered executing code from flash; core voltage 2.7 V; all peripherals enabled but not configured to run. ...
Page 45
... NXP Semiconductors Table 7. Core voltage 3 Peripheral RIT UART0 UART1 UART2 UART3 PWM1 Motor control PWM Quadrature encoder 2 I C0-bus 2 I C1-bus 2 I C2-bus 2 I S-interface (LPC1768/66/65 only) <tbd> SPI SSP0 SSP1 CAN1 CAN2 ADC DAC (LPC1768/66/65 only) USB Ethernet (LPC1768/66/64 only) GPDMA controller Table 8 ...
Page 46
... NXP Semiconductors 10.2 Electrical pin characteristics (X) Fig 10. Typical LOW-level output I (X) Fig 11. Typical HIGH-level output I LPC1768_66_65_64_2 Objective data sheet <tbd> Measured on pins Pn. x.x V. DD(3V3) current versus LOW-level output <tbd> Measured on pins Pn. x.x V. DD(3V3) ...
Page 47
... NXP Semiconductors (X) Fig 12. Typical pull-up current I (X) Fig 13. Typical pull-down current I LPC1768_66_65_64_2 Objective data sheet <tbd> Measured on pins Pn. x.x V. DD(3V3) versus input voltage <tbd> Measured on pins Pn. x.x V. DD(3V3) versus input voltage V pd Rev. 02 — ...
Page 48
... NXP Semiconductors 11. Dynamic characteristics 11.1 Flash memory Table 9. Flash characteristics +85 C unless otherwise specified. amb Symbol Parameter N endurance endu t retention time ret 11.2 External clock Table 10. Dynamic characteristic: external clock + amb DD(3V3) Symbol Parameter f oscillator frequency osc ...
Page 49
... NXP Semiconductors 11.3 Internal oscillators Table 11. Dynamic characteristic: internal oscillators + amb DD(3V3) Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...
Page 50
... NXP Semiconductors 2 11.4 I C-bus Table 12. Dynamic characteristic + amb DD(3V3) Symbol Parameter 2 I C-bus pins (P0[27] and P0[28]) t output fall time f(o) t rise time r t fall time f t bus free time between a STOP and BUF START condition t LOW period of the SCL clock ...
Page 51
... NXP Semiconductors 11.5 SSP interface Table 13. Dynamic characteristic: SSP interface + amb DD(3V3) Symbol Parameter SSP interface t SPI_MISO set-up time su(SPI_MISO) [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...
Page 52
... NXP Semiconductors 11.6 USB interface Table 14. Dynamic characteristics: USB pins (full-speed pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time matching FRFM V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition to SE0 ...
Page 53
... NXP Semiconductors 11.7 SPI Table 15. Dynamic characteristics of SPI pins +85 C. amb Symbol Parameter SPI master T SPI cycle time SPICYC t SPICLK HIGH time SPICLKH t SPICLK LOW time SPICLKL t SPI data set-up time SPIDSU t SPI data hold time SPIDH t SPI data output valid time ...
Page 54
... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 21. SPI master timing (CPHA = 0) SCK (CPOL = 0) SCK (CPOL = 1) MOSI MISO Fig 22. SPI slave timing (CPHA = 1) LPC1768_66_65_64_2 Objective data sheet T SPICYC t SPIQV DATA VALID MOSI t SPIDSU MISO DATA VALID T t SPICYC SPICLKH t SPIDSU DATA VALID ...
Page 55
... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SPI slave timing (CPHA = 0) LPC1768_66_65_64_2 Objective data sheet T SPICYC t SPIDSU MOSI DATA VALID t SPIQV MISO DATA VALID Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller t t SPICLKH SPICLKL t SPIDH DATA VALID t SPIOH DATA VALID 002aad989 © ...
Page 56
... NXP Semiconductors 11.8 Ethernet (LPC1768/66/64 only) Table 16. Dynamic characteristics: Ethernet MAC pins Symbol Parameter Ethernet MAC signals for MIIM T clock cycle time cy(clk) t data output valid time v(Q) t data output high-impedance time QZ t data input set-up time su(D) t data input hold time h(D) Ethernet MAC signals for RMII ...
Page 57
... NXP Semiconductors ENET_MDIO(O) ENET_MDIO(I) Fig 24. Ethernet MAC MIIM timing ENET_REF_CLK ENET_TX_EN ENET_TXD[1:0] ENET_CRS ENET_RXD[1:0] ENET_RX_ER Fig 25. Ethernet RMII timing LPC1768_66_65_64_2 Objective data sheet T cy(clk) ENET_MDC t v(Q) t d(QV su(D) h(D) Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller su(D) h(D) 002aad990 t h(Q) 002aad991 © NXP B.V. 2009. All rights reserved. ...
Page 58
... NXP Semiconductors 2 11.9 I S-bus interface (LPC1768/66/65 only) Table 17. Dynamic characteristics +85 C. amb Symbol Parameter Common to input and output T clock cycle time cy(clk) t fall time f t rise time r Output t pulse width HIGH WH t pulse width LOW WL t data output valid time ...
Page 59
... NXP Semiconductors I2SRX_CLK I2SRX_SDA I2SRX_WS Fig 27. I LPC1768_66_65_64_2 Objective data sheet T cy(clk S-bus timing (input) Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller su(D) h( su(D) su(D) © NXP B.V. 2009. All rights reserved 002aae159 ...
Page 60
... NXP Semiconductors 12. ADC electrical characteristics Table 18. ADC characteristics +85 C; unless otherwise specified; ADC frequency <tbd>. DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error ...
Page 61
... NXP Semiconductors 4095 4094 4093 4092 4091 4090 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
Page 62
... NXP Semiconductors AD0[y] Fig 29. Suggested ADC interface - LPC1768/66/65/64 AD0[y] pin LPC1768_66_65_64_2 Objective data sheet LPC17XX x k SAMPLE Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller R vsi AD0[y] V EXT 002aad949 © NXP B.V. 2009. All rights reserved ...
Page 63
... NXP Semiconductors 13. DAC electrical characteristics (LPC1768/66/65 only) Table 19. DAC electrical characteristics +85 C; unless otherwise specified; DAC frequency <tbd> MHz. DDA amb Symbol Parameter PSRR power supply rejection ratio V output voltage O E differential linearity error D E integral non-linearity ...
Page 64
... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC17xx Fig 30. LPC1768/66/65/64 USB interface on a self-powered device LPC17xx Fig 31. LPC1768/66/65/64 USB interface on a bus-powered device LPC1768_66_65_64_2 Objective data sheet LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller V DD(3V3) USB_UP_LED USB_CONNECT SoftConnect switch R1 1 BUS ...
Page 65
... NXP Semiconductors RSTOUT LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D Fig 32. LPC1768/66/65 USB OTG port configuration USB_UP_LED USB_D+ USB_D LPC17xx USB_PWRD USB_OVRCR USB_PPWR Fig 33. LPC1768/66/65 USB host port configuration LPC1768_66_65_64_2 Objective data sheet RESET_N ADR/PSW OE_N/INT_N V DD ...
Page 66
... NXP Semiconductors USB_UP_LED USB_CONNECT LPC17xx USB_D+ USB_D V BUS Fig 34. LPC1768/66/65/64 USB device port configuration LPC1768_66_65_64_2 Objective data sheet Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller USB-B D connector V BUS 002aad943 © NXP B.V. 2009. All rights reserved. ...
Page 67
... NXP Semiconductors 15. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 68
... NXP Semiconductors 16. Abbreviations Table 20. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GPIO IRC IrDA JTAG MAC MIIM OHCI OTG PHY PLL PWM RIT RMII SE0 SPI SSI SSP TCM TTL UART USB LPC1768_66_65_64_2 Objective data sheet ...
Page 69
... NXP Semiconductors 17. Revision history Table 21. Revision history Document ID Release date LPC1768_66_65_64_2 20090211 • Modifications: • • LPC1768_66_65_64_1 20090115 LPC1768_66_65_64_2 Objective data sheet Data sheet status Objective data sheet Data sheet descriptive title: added ‘up to 512 kB flash’ Figure 3 “LPC1768/66/65/64 memory map” on page Table 9 “ ...
Page 70
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 71
... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . 14 7.1 Architectural overview 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 14 7.3 On-chip flash program memory . . . . . . . . . . . 15 7.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 Memory Protection Unit (MPU ...
Page 72
... NXP Semiconductors 10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 43 10.2 Electrical pin characteristics . . . . . . . . . . . . . . 46 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 48 11.1 Flash memory 11.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.3 Internal oscillators 11.4 I C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.5 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.6 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.8 Ethernet (LPC1768/66/64 only 11.9 I S-bus interface (LPC1768/66/65 only ADC electrical characteristics . . . . . . . . . . . . 60 13 DAC electrical characteristics (LPC1768/66/65 only Application information ...