lpc2377 NXP Semiconductors, lpc2377 Datasheet
lpc2377
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lpc2377 Summary of contents
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... ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC Rev. 04 — 19 November 2008 1. General description The LPC2377/78 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 512 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate ...
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... S port, and the Secure Digital/MultiMediaCard (SD/MMC) card 2 C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...
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... LQFP144 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) LPC2377FBD144 512 LPC2378FBD144 512 LPC2377_78_4 Product data sheet Description plastic low profile quad flat package; 144 leads; body 20 plastic low profile quad flat package; 144 leads; body 20 ...
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... A/D CONVERTER D/A CONVERTER AOUT VBAT 2 kB BATTERY RAM power domain 2 RTCX1 RTC RTCX2 OSCILLATOR ALARM WATCHDOG TIMER SYSTEM CONTROL (1) LPC2378 only. Fig 1. LPC2377/78 block diagram LPC2377_78_4 Product data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 32 kB 512 kB TEST/DEBUG FLASH INTERFACE ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2377/78 pinning 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD/ 66 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 67 I/O SCL1 O I I/O [1] P0[2]/TXD0 141 I/O O [1] P0[3]/RXD0 142 I/O I [1] P0[4]/ 116 I/O I2SRX_CLK/ I/O RD2/CAP2[ LPC2377_78_4 Product data sheet 1 108 LPC2377FBD144 LPC2378FBD144 36 002aac584 Description Port 0: Port 32-bit I/O port with individual direction controls for each bit ...
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... It is HIGH when the device is not configured or during global suspend. (LPC2378 only) MOSI1 — Master Out Slave In for SSP1. AD0[7] — A/D converter 0, input 7. Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller 2 S-bus specification . 2 S-bus specifi ...
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... I2SRX_CLK — Receive Clock driven by the master and received by the slave. Corresponds to the signal SCK in the I CAP3[0] — Capture input for Timer 3, channel 0. Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller 2 S-bus specification . © NXP B.V. 2008. All rights reserved. ...
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... ENET_RXD0 — Ethernet receive data. P1[10] — General purpose digital input/output pin. ENET_RXD1 — Ethernet receive data. P1[14] — General purpose digital input/output pin. ENET_RX_ER — Ethernet receive error. Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller 2 S-bus specification . 2 S-bus specification . ...
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... MAT0[0] — Match output for Timer 0, channel 0. P1[29] — General purpose digital input/output pin. PCAP1[1] — Capture input for PWM1, channel 1. MAT0[1] — Match output for Timer 0, channel 0. Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...
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... P2[6] — General purpose digital input/output pin. PCAP1[0] — Capture input for PWM1, channel 0. RI1 — Ring Indicator input for UART1. TRACEPKT1 — Trace Packet, bit 1. Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...
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... D0 — External memory data line 0. P3[1] — General purpose digital input/output pin. D1 — External memory data line 1. P3[2] — General purpose digital input/output pin. D2 — External memory data line 2. Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller 2 S-bus specification . 2 S-bus specification . ...
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... A5 — External memory address line 5. P4[6] — General purpose digital input/output pin. A6 — External memory address line 6. P4[7] — General purpose digital input/output pin. A7 — External memory address line 7. Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...
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... ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated. USB_D 2 — USB2 port bidirectional D line. LPC2378 only. This pin is not connected on the LPC2377. DBGEN — JTAG interface control signal. Also used for boundary scanning. TDO — Test Data out for JTAG interface. ...
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... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2377/78 being in Reset state. external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...
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... The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2377/78 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. ...
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... The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at SRAM speeds of 72 MHz. The LPC2377/78 provides a minimum of 100000 write/erase cycles and 20 years of data retention. 7.3 On-chip SRAM The LPC2377/78 includes a SRAM memory reserved for the ARM processor exclusive use ...
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... NXP Semiconductors 3.75 GB Fig 3. LPC2377/78 memory map 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... External memory controller The LPC2377/78 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals ...
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... Output enable and write enable delays – Extended wait 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2377/78 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination ...
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... The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2377/78 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip ...
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... Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. LPC2377_78_4 Product data sheet Single-chip 16-bit/32-bit microcontroller Rev. 04 — 19 November 2008 LPC2377/78 © NXP B.V. 2008. All rights reserved ...
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... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC2377/78 can enter one of the reduced power modes and wake USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...
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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • Full CAN messages can generate interrupts. 7.13 10-bit ADC The LPC2377/78 contains one ADC single 10-bit successive approximation ADC with eight channels. 7.13.1 Features • 10-bit successive approximation ADC • ...
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... UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2377/78 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...
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... The I be controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2377/78 supports bit rates up to 400 kbit/s (Fast 2 I C-bus). 7.19.1 Features • ...
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... Controls include reset, stop and mute options separately for I 7.21 General purpose 32-bit timers/external event counters The LPC2377/78 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2377/78. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2377/78, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider ...
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... The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2377/78 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. LPC2377_78_4 ...
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... PLL to lock, then connect to the PLL as a clock source. 7.25.3 Wake-up timer The LPC2377/78 begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...
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... Each of the peripherals has its own clock divider which provides even better power control. The LPC2377/78 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the battery RAM ...
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... System control 7.26.1 Reset Reset has four sources on the LPC2377/78: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in timer” ...
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... Code security (Code Read Protection - CRP) This feature of the LPC2377/78 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location ...
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... AHB2 are the ARM7 and the Ethernet block. 7.26.5 External interrupt inputs The LPC2377/78 includes edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. ...
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... lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2377/78 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. ...
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... V tolerant I/O pins; only valid when the V DD(3V3) supply voltage is present [2][3] other I/O pins per supply pin per ground pin based on package heat transfer, not device power consumption human body model; all pins Rev. 04 — 19 November 2008 LPC2377/78 Min Max Unit 3.0 3.6 V 3.0 3.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4 ...
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... 0 DD(3V3 0 DDA < V < DD(3V3) I Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 [2] 2.0 3.3 3.6 2.5 3.3 V DDA - - 100 ...
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... CCLK = 72 MHz all peripherals enabled; PCLK = CCLK CCLK = 10 MHz CCLK = 72 MHz V = 3.3 V; DD(DCDC)(3V3 amb OLS DD(3V3 < V < 3 Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller [1] Min Typ Max - 125 - - 150 ...
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... V range 1 3 GND L pin to GND with 33 series resistor; steady state drive SoftConnect = ON drops below 1 grounded. DD(3V3 and D . Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller [1] Min Typ Max 0 0.8 - 2.5 0 0.18 2 ...
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... See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 4. Figure Figure 4. Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller Min Typ ...
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... Product data sheet (2) (5) (4) (3) 1 LSB (ideal) 1018 (LSB ) ia ideal ). D ). Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller offset error E O (1) 1019 1020 1021 1022 1023 1024 V V DDA SSA 1 LSB = 1024 002aab136 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors AD0[y] Fig 5. Suggested ADC interface - LPC2377/78 AD0[y] pin LPC2377_78_4 Product data sheet LPC23XX 20 k SAMPLE Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller R vsi AD0[y] V EXT 002aac610 © NXP B.V. 2008. All rights reserved ...
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... EOP; see Figure 9 must accept as EOP; see Figure 9 over specified ranges. DD(3V3) Conditions amb measured in SPI Master mode; see Figure 10 Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller Min Typ Max 8.5 - 13.8 7 109 1.3 - 2.0 160 - 175 2 ...
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Table 9. Dynamic characteristics: Static external memory interface pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write cycles t CS LOW to address valid CSLAV ...
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Table 9. Dynamic characteristics: Static external memory interface pF amb DD(DCDC)(3V3) Symbol Parameter Conditions t WE HIGH to data invalid WEHDNV time t BLS HIGH to address BLSHANV ...
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... Fig 7. External memory read access LPC2377_78_4 Product data sheet t t CHCL CLCX T cy(clk) = 200 mV) i(RMS) t CSLAV OELAV t OELOEH t BLSLAV Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller t CHCX t CLCH 002aaa907 t CSHOEH t h(D) t OEHANV t CSHBLSH 002aad955 © NXP B.V. 2008. All rights reserved ...
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... BLSLBLSH t t CSLBLSL WELDV t CSLDV crossover point crossover point differential data to SE0/EOP skew PERIOD FDEOP Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller t WEHANV t BLSHANV t WEHDNV t BLSHDNV extended source EOP width: t receiver EOP width: t 002aad956 FEOPT , t EOPR1 EOPR2 002aab561 © ...
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... Fig 11. LPC2378 USB interface on a self-powered device LPC2377_78_4 Product data sheet Single-chip 16-bit/32-bit microcontroller t su(SPI_MISO) V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1 BUS USB_D USB_D V SS Rev. 04 — 19 November 2008 LPC2377/78 sampling edges 002aad326 USB-B connector 002aac578 © NXP B.V. 2008. All rights reserved ...
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... LPC23XX Fig 12. LPC2378 USB interface on a bus-powered device LPC2377_78_4 Product data sheet Single-chip 16-bit/32-bit microcontroller V DD(3V3 USB_UP_LED 1 BUS USB_D USB_D V SS Rev. 04 — 19 November 2008 LPC2377/78 USB-B connector 002aac579 © NXP B.V. 2008. All rights reserved ...
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... scale (1) ( 0.20 20.1 20.1 22.15 22.15 0.5 0.09 19.9 19.9 21.85 21.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller detail 0.75 1.4 1 0.2 0.08 0.08 0.45 1.1 EUROPEAN PROJECTION SOT486 ...
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... Reduced Media Independent Interface Request To Send Single Ended Zero Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...
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... Typ to Min column. hys characteristics” added I characteristics”, updated Table 9 “Dynamic characteristics: Static external memory Figure 7 “External memory read access” Figure 1 “LPC2377/78 block diagram”. Preliminary data sheet Preliminary data sheet . DD(1V8) Preliminary data sheet Rev. 04 — 19 November 2008 ...
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... I C-bus — logo is a trademark of NXP B.V. SoftConnect — trademark of NXP B.V. GoodLink — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 04 — 19 November 2008 LPC2377/78 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...
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... Dynamic characteristics . . . . . . . . . . . . . . . . . 43 10.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 Application information . . . . . . . . . . . . . . . . . 48 11.1 Suggested USB interface solutions (LPC2378 only Package outline . . . . . . . . . . . . . . . . . . . . . . . . 50 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 52 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 53 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 53 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15.3 Disclaimers Rev. 04 — 19 November 2008 LPC2377/78 continued >> © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 19 November 2008 Document identifier: LPC2377_78_4 ...