lpc3240 NXP Semiconductors, lpc3240 Datasheet - Page 30

• Manufacturer Part Number: lpc3240
• Description: 16/32-bit Arm Microcontrollers; Hardware ?oating-point Coprocessor, Usb On-the-go, And Emc Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3220_30_40_50_1
Preliminary data sheet
7.6.4.1 Features
7.6.4 LCD controller
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for
dual-role devices under software control. HNP is partially implemented in hardware.
Provides programmable timers required for HNP and SRP.
Supports slave mode operation through AHB slave interface.
Supports the OTG ATX from NXP (ISP 1302) or any external CEA-2011OTG
specification compliant ATX.
AHB bus master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
Supports single and dual-panel color STN displays.
Supports Thin Film Transistor (TFT) color displays.
Programmable display resolution including, but not limited to: 320
640
Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32 k color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized, for color STN and TFT.
24 bpp true-color non-palettized, for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.
LCD panel clock may be generated from the peripheral clock or from a clock input pin.
200, 640
240, 640
Rev. 01 — 6 February 2009
480, 800
600, and 1024
LPC3220/30/40/50
32 bit RAM.
16/32-bit ARM microcontrollers
768.
© NXP B.V. 2009. All rights reserved.
200, 320
30 of 73
240,
768