p89c538nbbb NXP Semiconductors, p89c538nbbb Datasheet - Page 25

• Manufacturer Part Number: p89c538nbbb
• Description: Cmos Single-chip 8-bit Microcontrollers With Flash Program Memory
• Manufacturer: NXP Semiconductors

1. V
2. Read operation withVPP = V
3. With V
4. Refer to Table 38 for valid Data–In during a write operation.
5. X can be V
Philips Semiconductors
Table 10.
NOTES:
Set–Up Automatic Chip Erase/Erase Commands
The automatic chip erase does not require the device to be entirely
pre–programmed prior to executing the Automatic set–up erase
command and automatic chip erase command. Upon executing the
Automatic chip erase command, the device automatically will
program and verify the entire memory for an all–zero data pattern.
When the device is automatically verified to contain an all–zero
pattern, a self–timed chip erase and verify begins. The erase and
verify operations are complete when the data on DQ7 is”1” at which
time the device returns to the standby mode. The system is not
required to provide any control or timing during these operations.
When using the Automatic Chip Erase algorithm, note that the erase
automatically terminates when adequate erase margin has been
achieved for the memory array (no erase verify command is
required). The margin voltages are internally generated in the same
manner as when the standard erase verify command is used.
The Automatic set–up erase command is a command only operation
that stages the device for automatic electrical erasure of all bytes in
the array. Automatic set–up erase is performed by writing 30H to the
command register.
To command automatic chip erase, the command 30H must be
written again to the command register. The automatic chip erase
begins on the rising edge of the WE and terminates when the data
on DQ7 is ”1 “ and the data on DQ6 stops toggling for two
consecutive read cycles, at which time the device returns to the
standby mode.
Set–Up Automatic Program/Program Commands
The Automatic Set–up Program is a command–only operation that
stages the devices for automatic programming. Automatic Set–up
Program is performed by writing 40H to the command register.
Once the Automatic Set–up Program operation is performed, the
next WE pulse causes a transition to an active programming
operation. Addresses are internally latched on the falling edge of the
WE pulse. Data is internally latched on the rising edge of the WE
pulse. The rising edge of WE also begins the programming
operation. The system is not required to provide further controls or
timings. The device will automatically provide an adequate internally
generated program pulse and verify margin. The automatic
programming operation is completed when the data read on DQ6
stops toggling for two consecutive read cycles and the data on DQ7
and DQ6 are equivalent to data written to these two bits at which
time the device returns to the Read mode (no program verify
command is required; but data can be read out if OE is active low).
1997 Jun 05
READ/WRITE
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
OPERATION
PPH
is the programming voltage specified for the device.
PP
at high voltage, the standby current equals I
IL
or V
IH
Read(2)
Standby(4)
Write
.
PPH
may access array data (if write command is preceded) or silicon ID codes.
V
V
V
PPH
PPH
PPH
V
PP
(1)
CC
+I
PP
V
V
V
IL
IH
IL
(standby).
CE
25
Reset Command
A reset command is provided as a means to safely abort the erase–
or program–command sequences. Following either set–up
command (erase or program) with two consecutive writes of FFH
will safely abort the operation. Memory contents will not be altered.
Should program–fail or erase–fail happen, two consecutive writes of
FFH will reset the device to abort the operation. A valid command
must then be written to place the device in the desired state.
Write Operation Status
Toggle Bit–DQ6
The 89C535/536/538 features a “Toggle Bit” as a method to indicate
to the host system that the Auto Program/Erase algorithms are
either in progress or completed.
While the Automatic Program or Erase algorithm is in progress,
successive attempts to read data from the device will result in DQ6
toggling between one and zero. Once the Automatic Program or
Erase algorithm is completed, DQ6 will stop toggling and valid data
will be read. The toggle bit is valid after the rising edge of the
second WE pulse of the two write pulse sequences.
Data Polling–D07
The 89C535/536/538 also features DATA Polling as a method to
indicate to the host system that the Automatic Program or Erase
algorithms are either in progress or completed.
While the Automatic Programming algorithm is in operation an
attempt to read the device will produce the complement data of the
data last written to DQ7. Upon completion of the Automatic Program
algorithm an attempt to read the device will produce the true data
last written to DQ7. The Data Polling feature is valid after the rising
edge of the second WE pulse of the two write pulse sequences.
While the Automatic Erase algorithm is in operation, DQ7 will read
“0” until the erase operation is completed. Upon completion of the
erase operation, the data on DQ7 will read “1”. The DATA Polling
feature is valid after the rising edge of the second WE pulse of two
writes pulse sequences.
The DATA Polling feature is active during Automatic Program/Erase
algorithms.
Write Operation
The data to be programmed into Flash should be inverted when
programming. In other words to program the value ‘00’, ‘FF’ should
be applied to port P0.
V
X
V
IL
IH
OE
89C535/89C536/89C538
VI
X
V
IL
H
WE
Preliminary specification
DATA OUT(3)
Tri–State
Data In(5)
D00–D07