lh7a400 NXP Semiconductors, lh7a400 Datasheet
lh7a400
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lh7a400 Summary of contents
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... V ± • Operating Temperature: −40°C to +85°C • 256-ball BGA or 256-ball LFBGA Package DESCRIPTION The LH7A400, powered by an ARM922T com- plete System-on-Chip with a high level of integration to satisfy a wide range of requirements and expectations. This high degree of integration lowers overall system costs, reduces development cycle time and accelerates product introduction ...
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... LH7A400 Type number LH7A400N0G000B5 BGA256 LH7A400N0F000B3A LFBGA256 LH7A400N0F000B5 LFBGA256 LH7A400N0F076B5 LFBGA256 2 NXP Semiconductors Table 2. Ordering information Package Name Description plastic ball grid array package; 256 balls plastic low profile fine-pitch ball grid array package; 256 balls plastic low profile fine-pitch ball grid array package ...
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... RESET CONTROL INTERRUPT CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE 80KB SRAM DMA CONTROLLER ADVANCED ADVANCED PERPHERAL BUS (AHB) BUS (APB) Figure 1. LH7A400 block diagram Rev. 01 — 16 July 2007 LH7A400 LH7A400 REAL TIME CLOCK WATCHDOG TIMER TIMER (3) GENERAL PURPOSE I/O (60) SYNCHRONOUS SERIAL PORT BATTERY ...
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... Transparent top view Figure 2. Pin configuration (BGA256) LH7A400 ball A1 index area Transparent top view Figure 3 ...
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... Core Power L13 J4 E15 J8 D12 T10 L4 N15 L9 VSSC Core Ground H12 N3 B15 N7 C9 N10 G6 R5 Preliminary data sheet NXP Semiconductors Table 3. Functional Pin List RESET DESCRIPTION STATE Rev. 01 — 16 July 2007 LH7A400 STANDBY OUTPUT I/O NOTES STATE DRIVE 5 ...
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... LH7A400 BGA LFBGA SIGNAL PIN PIN R11 P12 VDDA Analog Power for PLL N12 M10 P12 R13 VSSA Analog Ground for PLL T11 N11 D3 E4 nPOR Power On Reset User Reset; should be pulled HIGH for normal nURESET JTAG operation WAKEUP ...
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... Sync Memory Chip Select 0 Preliminary data sheet NXP Semiconductors Table 3. Functional Pin List (Cont’d) DESCRIPTION LOW: A25 LOW: A26 LOW: A27 LOW: CS6 LOW: CS7 Rev. 01 — 16 July 2007 LH7A400 RESET STANDBY OUTPUT I/O NOTES STATE STATE DRIVE LOW LOW 12 mA ...
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... LH7A400 BGA LFBGA SIGNAL PIN PIN D13 A15 nSCS1 Sync Memory Chip Select 1 E11 D11 nSCS2 Sync Memory Chip Select 2 A12 E10 nSCS3 Sync Memory Chip Select 3 C12 A13 nSWE Sync Memory Write Enable C11 B11 nCAS Sync Memory Column Address Strobe Signal ...
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... Input: PE1 Input: PE2 Input: PE3 Input: PF0 Input: PF1 Input: PF2 Input: PF3 Input: PF4 Input: PF5 Input: PF6 Input: PF7 LOW: PG0 LOW: PG1 Rev. 01 — 16 July 2007 LH7A400 RESET STANDBY OUTPUT I/O NOTES STATE STATE DRIVE No Change 12 mA I/O No Change 12 mA I/O ...
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... LH7A400 BGA LFBGA SIGNAL PIN PIN • GPIO Port G PG2 • I/O Read Strobe for PC Card (PCMCIA or CF) in nPCIOR single or dual card mode • GPIO Port G PG3 • I/O Write Strobe for PC Card (PCMCIA or CF) in nPCIOW single or dual card mode • GPIO Port G ...
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... SSPFRM Synchronous Serial Port Frame Sync nSSPFRM Preliminary data sheet NXP Semiconductors Table 3. Functional Pin List (Cont’d) DESCRIPTION LCDENAB MMCCLK MMCCMD MMCDATA Rev. 01 — 16 July 2007 LH7A400 RESET STANDBY OUTPUT I/O NOTES STATE STATE DRIVE LOW: LOW LOW LOW ...
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... LH7A400 BGA LFBGA SIGNAL PIN PIN F6 G2 COL0 F5 G1 COL1 G1 H3 COL2 G2 H5 COL3 Keyboard Interface G4 H6 COL4 G5 H7 COL5 H1 H2 COL6 H2 H1 COL7 H3 J1 TBUZ Timer Buzzer (254 kHz MAX.) Boot Device Media Change. Used with WIDTH0 C3 F5 MEDCHG and WIDTH1 to specify boot memory device. ...
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... MUSTN4 CUSTN4 MUSTN3 MUSTN3 MUSTN3 CUSTN3 MUSTN2 MUSTN2 MUSTN2 CUSTN2 MUSTN1 MUSTN1 MUSTN1 CUSTN1 MUSTN0 MUSTN0 MUSTN0 CUSTN0 Rev. 01 — 16 July 2007 LH7A400 COLOR AD-TFT/ TFT HR-TFT DUAL PANEL LOW LOW CLSTN7 Intensity Intensity CLSTN6 BLUE4 BLUE4 CLSTN5 BLUE3 BLUE3 CLSTN4 ...
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... LH7A400 Table 6. 256-Ball BGA Package Numerical Pin List BGA PIN SIGNAL A1 TDI A2 MMCDATA/MMSPIDOUT A3 MMCCLK/MMSPICLK A4 ACIN A5 VSS A6 PF0/INT0 A7 VDDC A8 A27/SCRST A9 DQM0 A10 SCLK A11 VSS A12 nSCS3 A13 A24 A14 D24 A15 A23 A16 D23 B1 TCK B2 TDO B3 MMCCMD/MMSPIDIN B4 ACSYNC B5 PF4/INT4/SCVCCEN B6 PF1/INT1 B7 PWM1 ...
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... K11 nCS0 K12 D7 K13 VSS K14 A5/SA3 K15 A4/SA2 K16 A3/SA1 L1 PA5 L2 PA6 L3 PA7 L4 PB0/UARTRX1 L5 PB1/UARTTX3 L6 PG2/nPCIOR L7 PB2/UARTRX3 L8 PC4/LCDSPS L9 VSSC L10 PE0/LCDVD4 L11 PD1/LCDVD9 L12 D0 L13 VDDC L14 D5 L15 D4 L16 D3 M1 VDD M2 PB3/UARTCTS3 M3 VSSC Rev. 01 — 16 July 2007 LH7A400 SIGNAL 15 ...
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... LH7A400 Table 6. 256-Ball BGA Package Numerical Pin List (Cont’d) BGA PIN SIGNAL M4 PB4/UARTDCD3 M5 VDD M6 PG3/nPCIOW M7 PG5/nPCCE1 M8 PG6/nPCCE2 M9 PE2/LCDVD6 M10 PE3/LCDVD7 M11 PD0/LCDVD8 M12 nCS3/nMMSPICS M13 A2/SA0 M14 VDD M15 D1 M16 A0/nWE1 N1 PB5/UARTDSR3 N2 PB6/SWID/SMBD N3 PB7/SMBCLK N4 PG7/PCDIR N5 VSS N6 PG4/nPCREG N7 PH3/CFA9/PCMCIAA25/nPCSLOTE2 N8 LCDVD3 N9 LCDDCLK ...
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... A19 D16 D18 E1 UARTCTS2 E2 WAKEUP E3 BATOK E4 nPOR E5 TDI E6 ACIN E7 PF2/INT2 E8 VSS E9 CS6/SCKE1_2 E10 nSCS3 E11 A24 E12 D22 E13 D20 E14 A18 E15 D17 E16 A16/SB0 F1 UARTTX2 F2 nPWRFL F3 UARTDCD2 F4 VDDC F5 MEDCHG F6 nBATCHG F7 VSS F8 nWE0 F9 VDD Rev. 01 — 16 July 2007 LH7A400 SIGNAL 17 ...
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... LH7A400 Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN SIGNAL F10 VDDC F11 VDD F12 D19 F13 A17/SB1 F14 VDD F15 D16 F16 A15/SA13 G1 COL1 G2 COL0 G3 UARTRX2 G4 UARTDSR2 G5 UARTIRTX1 G6 UARTIRRX1 G7 VSSC G8 VDD G9 D13 G10 A13/SA11 G11 A14/SA12 G12 D15 G13 ...
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... R11 PD5/LCDVD13 R12 PD6/LCDVD14 R13 VSSA R14 XTALIN R15 XTALOUT R16 USBDN T1 PG1/nPCWE T2 PG4/nPCREG T3 PG7/PCDIR T4 PH1/CFA8/PCRESET2 T5 PH3/CFA9/PCMCIAA25/nPCSLOTE2 T6 PH7/nPCSTATRE T7 LCDFP T8 LCDVD3 T9 PE0/LCDVD4 T10 PE2/LCDVD6 T11 PD3/LCDVD11 T12 PD4/LCDVD12 T13 PD7/LCDVD15 T14 WIDTH0 T15 WIDTH1 T16 USBDP Rev. 01 — 16 July 2007 LH7A400 SIGNAL 19 ...
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... This generated 1 Hz clock is used in the Real Time Clock counter. The 14.7456 MHz source is used to generate the main system clocks for the LH7A400 the source for PLL1 and PLL2, it acts as the primary clock to the peripherals and is the source clock to the Programma- ble clock (PGM) divider ...
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... Reset Modes There are three external signals that can generate resets to the LH7A400; these are nPOR (power on reset), nPWRFL (power failure) and nURESET (user reset). If any of these are active, a system reset is gen- erated internally. A nPOR reset performs a full system reset ...
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... Figure 6 shows the memory map of the LH7A400 system for the two boot modes. Once the LH7A400 has booted, the boot code can configure the ARM922T MMU to remap the low mem- ory space to a location in RAM. This allows the user to set the interrupt vector table ...
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... See Figure 7. Embedded SRAM The amount of Embedded SRAM contained in the LH7A400 is 80 kB. This Embedded memory is designed to be used for storing code, data, or LCD frame data and to be contiguous with external SDRAM. The large enough to store a QVGA panel (320 × ...
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... LH7A400 EXTERNAL TO INTERNAL TO THE LH7A400 THE LH7A400 SDRAM SRAM ADDRESS SDRAM ROM CONTROL Figure 7. External Bus Interface Block Diagram 24 NXP Semiconductors ARM922T ASYNCHRONOUS STATIC MEMORY CONTROLLER (SMC) EXTERNAL DATA PCMCIA/CF BUS SUPPORT INTERFACE (EBI) and SYNCHRONOUS DYNAMIC MEMORY CONTROLLER (SDMC) 80KB ...
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... Check for maximum duration of ATR character stream • Check for maximum time of receipt of first character of data stream • Check for maximum time allowed between characters • Character guard time • Block guard time • Transmit/receive character retry. Rev. 01 — 16 July 2007 LH7A400 25 ...
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... LCD panels. It interfaces directly to STN, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A400’s LCD Controller incorporates the timing con- version logic from TFT to HR- and AD-TFT, allowing a direct interface to these panels and minimizing external chip count ...
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... Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3. Timers Two identical timers are integrated in the LH7A400. Each of these timers has an associated 16-bit read/write data register and a control register. Each timer is loaded with the value written to the data register immediately, this value will then be decremented on the next active clock edge to arrive after the write ...
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... If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a System Reset. General Purpose I/O (GPIO) The LH7A400 GPIO has eight ports, each with a data register and a data direction register. It also has added registers including Keyboard Scan, PINMUX, GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI, and PGHCON ...
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... Using 14.7456 MHz Main Oscillator Crystal and 32.768 kHz RTC Oscillator Crystal 4. VDDC = 1. 1.89 V (LH7A400N0G000xx) ± 5. VDDC = 2 (LH7A400N0G076xx only) 6. VDD = 3 3.6 V (LH7A400N0G000xx) 7. VDD = 3.14V to 3.60 V (LH7A400N0G076xx only) 8. IMPORTANT: Most peripherals will NOT function with crystals other than 14.7456 MHz. Preliminary data sheet NXP Semiconductors MINIMUM MAXIMUM −0.3 V − ...
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... Clock Period (FCLK) NOTES: 1. Table 9 is representative of a typical wafer process. Guaranteed values are in the Recommended Operating Conditions table. 2. LH7A400N0G000xx 30 NXP Semiconductors ° TEMP ( C) (For LH7A400N0G000xx) 1.71 V 1.8 V 1.89 V 211 MHz 225 MHz 240 MHz 4.74 ns 4.44 ns 4.17 ns 200 MHz 212 MHz 227 MHz 5. ...
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... RATING UNIT 3.0 to 3.6 V 1.71 to 1.89 V VSS VDD/2 V Rev. 01 — 16 July 2007 LH7A400 CONDITIONS NOTES VIL to VIH − V IOH = 4 mA − V IOH = 8 mA − V IOH = IOL = IOL = IOL = 12 mA ...
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... LH7A400 CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make this data more usable, the values presented in Table 10 were derived under the condi- tions presented here. Maximum Specified Value The values specified in the MAXIMUM column were determined using these operating characteristics: • ...
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... ACBITCLK, AC97 clock • SCLK, Synchronous Memory clock. All signal transitions are measured at the 50 % point. For outputs from the LH7A400, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from a valid address bus, or rising edge of the peripheral clock. Maximum requirements for tOVXXX are shown in Table 12 ...
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... LH7A400 SIGNAL TYPE LOAD SYMBOL ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ [wait states × HCLK period]) Output 50 pF A[27:0] Output 50 pF — — Output 50 pF D[31:0] Input — nCS[7:0] Output 30 pF SA[13:0] Output 50 pF SA[17:16]/SB[1:0] Output 50 pF Output 50 pF D[31:0] Input nCAS Output 30 pF nRAS Output 30 pF nSWE ...
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... ACOUT Output 30 pF ACIN Input LCDVD [17:0] Output 30 pF NOTES: 1. Register BCRx:WST1 = 0b000 2. For Output Drive strength specifications, refer to Table 3 3. LH7A400N0G076xx only 4. LH7A400N0G000xx only Preliminary data sheet NXP Semiconductors MIN. MAX. MMC INTERFACE SIGNALS tOS 5 ns tOH 5 ns tOS 5 ns ...
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... Asynchronous Memory Read tWC VALID ADDRESS tDVWE, tDHWE, tDVBE tDHBE VALID DATA tAVCS tCS nCS Valid tAVWE tWE tCSHWE nWE Valid WRITE EDGE tAVBE tBEW tCSHBE nBLE Valid Rev. 01 — 16 July 2007 32-Bit System-on-Chip 4 tAHCS LH7A400-201 Preliminary data sheet ...
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... Figure 11. External Asynchronous Memory Write with 4 Wait States (BCRx:WST1 = 0b100) Preliminary data sheet NXP Semiconductors VALID ADDRESS VALID DATA nCSx Valid nWE Valid nBLE Valid WAIT WAIT WAIT WAIT STATE 1 STATE 2 STATE 3 STATE 4 tWS tWS tWS tWS Rev. 01 — 16 July 2007 LH7A400 7 8 WRITE EDGE LH7A400-203 37 ...
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... VALID ADDRESS VALID DATA tDSCS tAVCS tCS nCS Valid tDSOE tAVOE tOE nOE Valid tDSBE tAVBE tBER nBLE Valid Rev. 01 — 16 July 2007 32-Bit System-on-Chip 4 DATA LATCHED HERE tDHCS tDHOE tDHBE LH7A400-200 Preliminary data sheet ...
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... See Figure 16 and Figure 17. Rev. 01 — 16 July 2007 LH7A400 WAIT STATE 4 4 WAIT STATES, DATA LATCHED tWS HERE LH7A400-202 39 ...
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... COLUMN tOVA, tOVB DATA n DATA Figure 14. Synchronous Burst Read tOVC tOVXXX tOHXXX ACTIVE tOHA BANK, ROW tOVA Rev. 01 — 16 July 2007 32-Bit System-on-Chip DATA DATA LH7A400-23 WRITE BANK, COLUMN DATA tOVD tOHD LH7A400-24 Preliminary data sheet ...
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... MSB SSPTXD NOTE undefined. Figure 18. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 0 Preliminary data sheet NXP Semiconductors MSB LSB BITS MSB BITS BITS Rev. 01 — 16 July 2007 LH7A400 LH7A400-97 LSB LH7A400-98 LSB Q LSB LH7A400-99 41 ...
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... Figure 22. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 1 42 NXP Semiconductors MSB BITS BITS LSB MSB BITS LSB MSB BITS Rev. 01 — 16 July 2007 32-Bit System-on-Chip LSB MSB LH7A400-100 LSB Q LSB LH7A400-101 LSB MSB LH7A400-102 LSB MSB LH7A400-103 Preliminary data sheet ...
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... MSB NOTE undefined. Figure 25. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 1 Preliminary data sheet NXP Semiconductors BITS MSB LSB BITS BITS Rev. 01 — 16 July 2007 LH7A400 LSB Q LSB LH7A400-104 MSB LH7A400-105 Q LSB LSB LH7A400-106 43 ...
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... The returned data can bits in length, making the total frame length between bits. See Figure 26 and Figure 27. LSB 0 MSB LSB BITS OUTPUT DATA MSB LSB 8-BIT CONTROL LSB Rev. 01 — 16 July 2007 32-Bit System-on-Chip LH7A400-107 MSB LH7A400-108 Preliminary data sheet ...
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... None Preliminary data sheet NXP Semiconductors PRECHARGE ACCESS TIME TIME (See Note 1) (See Note 1) (See Note 1) ADDRESS tOVDREG tOHDREG tOVCEx tOHCEx tOVPCD tOHPCD DATA tISD tIHD tOVOE tOHOE Figure 28. PCMCIA Read Transfer Rev. 01 — 16 July 2007 LH7A400 HOLD TIME LH7A400-11 45 ...
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... ACCESS TIME TIME (See Note 1) (See Note 1) (See Note 1) ADDRESS tOVDREG tOHDREG tOVCEx tOHCEx tOVPCD DATA tOVD tOHD tOVWE tOHWE I/O Figure 29. PCMCIA Write Transfer ACCESS PRECHARGE Rev. 01 — 16 July 2007 32-Bit System-on-Chip HOLD TIME LH7A400-12 HOLD LH7A400-209 Preliminary data sheet ...
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... Figure 32 shows the waveforms and timing for the AC97 interface Data Setup and Hold. MMC CLOCK tIS tIH SOC INPUT DATA DATA/CMD tOS tOH INVALID DATA DATA /CMD tACBITCLK tOVAC97 tOHAC97 tISAC97 tIHAC97 Figure 32. AC97 Data Setup and Hold Rev. 01 — 16 July 2007 LH7A400 INVALID LH7A400-14 LH7A400-16 47 ...
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... Audio Codec Interface Waveforms Figure 33 and Figure 34 show the timing for the ACI. Transmit data is clocked on the rising edge of ACBIT- CLK (whether transmitted by the LH7A400 ACI or by the external codec chip); receive data is clocked on the fall- ing edge. This allows full-speed, full duplex operation. ...
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... System-on-Chip Figure 36. STN Horizontal Timing Diagram Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH7A400 49 ...
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... LH7A400 50 NXP Semiconductors Figure 37. STN Vertical Timing Diagram Rev. 01 — 16 July 2007 32-Bit System-on-Chip Preliminary data sheet ...
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... System-on-Chip Preliminary data sheet NXP Semiconductors Figure 38. TFT Horizontal Timing Diagram Rev. 01 — 16 July 2007 LH7A400 51 ...
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... LH7A400 52 NXP Semiconductors Figure 39. TFT Vertical Timing Diagram Rev. 01 — 16 July 2007 32-Bit System-on-Chip Preliminary data sheet ...
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... AD-TFT or HR-TFT HORIZONTAL LINE TIMING0:HSW 001 002 003 004 005 006 007 008 PIXEL DATA TIMING0:HSW + TIMING0:HBP 001 002 003 004 005 006 1 LCDDCLK ALITIMING2:SPLDEL 1 LCDDCLK ALITIMING1:LPDEL ALITIMING1:PSCLS ALITIMING2:PS2CLS2 ALITIMING1:REVDEL Rev. 01 — 16 July 2007 LH7A400 320 317 318 319 320 LH7A400-111 53 ...
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... Figure 41. AD-TFT and HR-TFT Vertical Timing Diagram CLOCK AND STATE CONTROLLER (CSC) WAVEFORMS Figure 42 shows the behavior of the LH7A400 when coming out of Reset or Power On. Figure 43 shows exter- nal reset timing, and Table 13 gives the timing parame- ters. Figure 44 depicts signal timing following a Reset. ...
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... WAKEUP (asynchronous) CLKEN HCLK Preliminary data sheet NXP Semiconductors tOSC14 Figure 42. Oscillator Start-up tURESET tPWRFL Figure 43. External Reset ≤ 7.8125 ms 7.8125 ms START UP Figure 44. Signal Timing After Reset Rev. 01 — 16 July 2007 LH7A400 LH7A400-25 LH7A400-26 STABLE CLOCK LH7A400-175 55 ...
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... LH7A400 INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 NOTES parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 12.5 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance ...
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... System-on-Chip INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 NOTES parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance ...
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... Power consumption may be higher than expected until software completes programming the GPIO. Some LH7A400 inputs have internal pull- ups or pull-downs. If unused, these inputs do not require external conditioning. OTHER CIRCUIT BOARD LAYOUT PRACTICES All outputs have fast rise and fall times ...
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... 1 scale 15.75 17.2 15. 14.75 16.8 14.75 REFERENCES JEDEC JEITA Rev. 01 — 16 July 2007 SOT1018 detail 0.25 0.1 0.15 0.35 EUROPEAN ISSUE DATE PROJECTION 07-07-07 07-07-07 LH7A400 59 ...
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... LH7A400 LFBGA256: plastic low profile fine-pitch ball grid array package; 256 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 1.35 0.5 14.1 mm 1.7 0.3 1.15 13.9 0.4 OUTLINE VERSION ...
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... REVISION HISTORY Document ID Release date Data sheet status LH7A400_N_1 20070716 Preliminary data sheet Modifications: • First NXP version based on the LH7A400 data sheet of 20070509 Preliminary data sheet NXP Semiconductors Table 14. Revision history Change notice Supersedes - FAST LH7A400 v1-5 5-9-07 Rev. 01 — 16 July 2007 ...
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... LH7A400 1. Legal information 1.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. ...
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... Dear customer from June 1 , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. ...
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... Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors ...
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... The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage ...