z8f0813 ZiLOG Semiconductor, z8f0813 Datasheet - Page 163
z8f0813
Manufacturer Part Number
z8f0813
Description
High-performance 8-bit Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z8F0813.pdf
(247 pages)
- Current page: 163 of 247
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PS024314-0308
Note:
Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
DEBUG Mode
The operating characteristics of the devices in DEBUG mode are:
•
•
•
•
•
Entering DEBUG Mode
The device enters DEBUG mode following the operations below:
•
•
Holding the DBG pin Low for an additional 5000 (minimum) clock cycles after reset
(making sure to account for any specified frequency error if using an internal oscillator)
prevents a false interpretation of an Autobaud sequence (see
Generator
•
RS-232 TX
RS-232 RX
pin, the DBG feature is unlocked. After releasing PA2/RESET, it is pulled high. At this
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute
specific instructions
The system clock operates unless in STOP mode
All enabled on-chip peripherals operate unless in STOP mode
Automatically exits HALT mode
Constantly refreshes the Watchdog Timer, if enabled.
The device enters DEBUG mode after the eZ8 CPU executes a
tion
If the DBG pin is held Low during the most recent clock cycle of System Reset, the part
enters DEBUG mode upon exiting System Reset
If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/DBG
on page 154).
Transceiver
RS-232
Open-Drain
Buffer
VDD
Z8 Encore! XP
10 k
Ω
OCD Auto-Baud Detector/
DBG Pin
Product Specification
BRK
(breakpoint) instruc-
®
On-Chip Debugger
F0823 Series
153
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