z8f0813 ZiLOG Semiconductor, z8f0813 Datasheet - Page 42
z8f0813
Manufacturer Part Number
z8f0813
Description
High-performance 8-bit Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z8F0813.pdf
(247 pages)
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HALT Mode
Peripheral-Level Power Control
Power Control Register Definitions
PS024314-0308
Executing the eZ8 CPU’s
powers down the CPU but leaves all other peripherals active. In HALT mode, the
operating characteristics are:
•
•
•
•
•
•
•
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
•
To minimize current in HALT mode, all GPIO pins that are configured as inputs must be
driven to one of the supply rails (V
In addition to the STOP and HALT modes, it is possible to disable each peripheral on each
of the Z8 Encore! XP F0823 Series devices. Disabling a given peripheral minimizes its
power consumption.
The following sections describe the power control registers.
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
Primary oscillator is enabled and continues to operate.
System clock is enabled and continues to operate.
eZ8 CPU is stopped.
Program counter stops incrementing.
Watchdog Timer’s internal RC oscillator continues to operate.
If enabled, the Watchdog Timer continues to operate.
All other on-chip peripherals continue to operate.
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
Voltage Brownout reset
External RESET pin assertion
HALT
instruction places the device into HALT mode, which
CC
or GND).
Z8 Encore! XP
Product Specification
®
Low-Power Modes
F0823 Series
32
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