str755fvx STMicroelectronics, str755fvx Datasheet - Page 6

• Manufacturer Part Number: str755fvx
• Description: Arm7tdmi-s, 32-bit Mcu With Flash, Smi, 3 Std 16-bit Timers Pwm Timer, Fast 10-bit Adc, I2c, Uart, Ssp, Usb And Can
• Manufacturer: STMicroelectronics

Introduction
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In SLOW mode, the AHB clock can be significantly decreased to reduce power
consumption.
The built-in Clock Controller also provides the 48 MHz USB clock directly without any extra
oscillators or PLL. For instance, starting from the 4 MHz crystal source, it is possible to
obtain in parallel 60 MHz for the AHB clock, 48 MHz for the USB clock and 30 MHz for the
APB peripherals.
Boot modes
At start-up, boot pins are used to select one of five boot options:
G
G
G
G
Booting from SMI memory allows booting from a serial flash. This way, a specific boot
monitor can be implemented. Alternatively, the STR750F can boot from the internal boot
loader that implements a boot from UART.
Power Supply Schemes
You can connect the device in any of the following ways depending on your application.
G
G
G
G
Caution: When powered by 5.0V, the USB peripheral cannot operate.
Boot from internal flash
Boot from external serial Flash memory
Boot from internal boot loader
Boot from internal SRAM
Power Scheme 1: Single external 3.3V power source. In this configuration the
V
regulator and the V
regulator. This scheme has the advantage of requiring only one 3.3V power source.
Power Scheme 2: Dual external 3.3V and 1.8V power sources. In this configuration,
the internal voltage regulators are switched off by forcing the VREG_DIS pin to high
level. V
V
for applications which already provide an 1.8V power supply.
Power Scheme 3: Single external 5.0V power source. In this configuration the
V
regulator and the V
regulator. This scheme has the advantage of requiring only one 5.0V power source.
Power Scheme 4: Dual external 5.0V and 1.8V power sources. In this configuration,
the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high
level. V
V
CORE
BACKUP
CORE
BACKUP
supply required for the internal logic is generated internally by the main voltage
CORE
supply required for the internal logic is generated internally by the main voltage
CORE
through the V
through the V
is provided externally through the V
is provided externally through the V
BACKUP
BACKUP
18_BKP
18_BKP
supply is generated internally by the low power voltage
supply is generated internally by the low power voltage
pin. This scheme is intended to save power consumption
pin. This scheme is intended to provide 5V I/O capability.
18
18
and V
and V
18REG
18REG
power pins and
power pins and
STR750F