str755fvx STMicroelectronics, str755fvx Datasheet - Page 61
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str755fvx
Manufacturer Part Number
str755fvx
Description
Arm7tdmi-s, 32-bit Mcu With Flash, Smi, 3 Std 16-bit Timers Pwm Timer, Fast 10-bit Adc, I2c, Uart, Ssp, Usb And Can
Manufacturer
STMicroelectronics
Datasheet
1.STR755FVX.pdf
(73 pages)
- Current page: 61 of 73
- Download datasheet (2Mb)
STR750F
3.3.10
Communication interface characteristics
I
Subject to general operating conditions for V
The ST7 I
described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 37.
1. f
2. Data based on standard I
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
2
t
w(STO:STA)
C - Inter IC control interface
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
t
t
t
su(STA)
period of SCL signal.
undefined region of the falling edge of SCL.
h(SDA)
r(SDA)
r(SCL)
f(SDA)
h(STA)
f(SCL)
PCLK
C
Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open-
Drain: when configured as open-drain, the PMOS connected between the I/O pin and
V
I/O pin and V
not possible to power off the STR7x while some another I
powered on: otherwise, the STR7x will be powered by the protection diode.
b
DD_IO
, must be at least 8 MHz to achieve max fast I
2
C interface meets the requirements of the Standard I
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
Capacitive load for each bus line
is disabled, but it is still present. Also, there is a protection diode between the
SDA and SCL characteristics
DD_IO
. Consequently, when using this I
2
C protocol requirement, not tested in production.
Parameter
DD_IO
2
C speed (400 kHz).
, f
PCLK
Standard mode
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
(2)
, and T
2
I
C in a multi-master network, it is
2
C
Max
1000
300
400
2
A
C master node remains
2
(2)
unless otherwise specified.
C communication protocol
20+0.1C
20+0.1C
Fast mode I
Electrical parameters
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
(4)
(2)
b
b
Max
900
300
300
400
2
C
(1)
(3)
(2)
Unit
61/71
pF
µs
ns
µs
µs
µs
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