mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 152

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.7
Port U is associated with the stepper stall detect (SSD1 and SSD0) and motor controller (MC1 and MC0)
modules. Each pin is assigned to these modules according to the following priority: SSD1/SSD0 >
MC1/MC0 > general-purpose I/O.
If SSD1 module is enabled, the PU[7:4] pins are controlled by the SSD1 module. If SSD1 module is
disabled, the PU[7:4] pins are controlled by the motor control PWM channels 3 and 2 (MC1).
If SSD0 module is enabled, the PU[3:0] pins are controlled by the SSD0 module. If SSD0 module is
disabled, the PU[3:0] pins are controlled by the motor control PWM channels 1 and 0 (MC0).
Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD
module and the motor control PWM channels respectively.
During reset, port U pins are configured as high-impedance inputs.
4.3.7.1
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRUx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is enabled, the associated
I/O register bit (PTUx) reads “1”.
If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is disabled, a read returns
the value of the pin.
152
SSD1/
SSD0:
Reset
MC:
W
R
M1SINP
M1C1P
Port U
PTU7
Port U I/O Register (PTU)
0
7
M1SINM
M1C1M
PTU6
0
6
Figure 4-43. Port U I/O Register (PTU)
M1COSP
M1COP
PTU5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
5
M1COSM
M1COM
PTU4
0
4
M0SINP
M0C1P
PTU3
0
3
M0SINM
M0C1M
PTU2
0
2
M1COSP
M0C0P
Freescale Semiconductor
PTU1
0
1
M0COSM
M0C0M
PTU0
0
0