mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 494

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 16 Timer Module (TIM16B8CV1)
16.3.2.16 Pulse Accumulator Flag Register (PAFLG)
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register.
494
PAOVF
Reset
Field
PAIF
1
0
W
R
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
This bit is cleared automatically by a write to the PAFLG register with bit 1 set.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set.
Any access to the PACNT register will clear all the flags in this register when TFFCA bit in register TSCR(0x0006)
is set.
0
0
7
Unimplemented or Reserved
Figure 16-25. Pulse Accumulator Flag Register (PAFLG)
0
0
6
Table 16-20. PAFLG Field Descriptions
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
0
0
4
Description
0
0
3
0
0
2
PAOVF
Freescale Semiconductor
0
1
PAIF
0
0