mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 301

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mc9s12e256

Manufacturer Part Number
mc9s12e256
Description
Hcs12 Microcontrollers 16-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of
tap2tap column in
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the
Freescale Semiconductor
SCL
SDA
SDA
SCL
START condition
Table
10-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used
Table
10-3, all subsequent tap points are separated by 2
Figure 10-5. SCL Divider and SDA Hold
MC9S12E256 Data Sheet, Rev. 1.08
Table 10-4. Multiplier Factor
SCL Hold(start)
IBC7-6
00
01
10
11
SCL Divider
RESERVED
MUL
01
02
04
STOP condition
Chapter 10 Inter-Integrated Circuit (IICV2)
SDA Hold
IBC5-3
Table
SCL Hold(stop)
as shown in the
10-4.
301

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