mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 74
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mc9s12e256
Manufacturer Part Number
mc9s12e256
Description
Hcs12 Microcontrollers 16-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12E256.pdf
(602 pages)
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1)
an external program (again through BDM commands). Note that if the part goes through a reset before the
security bits are reprogrammed to the unsecure state, the part will be secured again.
1.8
The microcontroller features three main low power modes. Consult the respective block description
chapter for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source
of information about the clock system is
1.8.1
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
1.8.2
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
1.8.3
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay
active. For further power consumption the peripherals can individually turn off their local clocks.
1.8.4
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
1.9
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. System resets can be generated through external control of the RESET pin, through the clock
and reset generator module CRG or through the low voltage reset (LVR) generator of the voltage regulator
module. Refer to
Voltage Regulator (VREG3V3V2)”
1.9.1
Table 1-9
74
Low Power Modes
Resets and Interrupts
lists interrupt sources and vectors in default order of priority.
Stop
Pseudo Stop
Wait
Run
Vectors
Chapter 4, “Clocks and Reset Generator (CRGV4)”
for detailed information on reset generation.
MC9S12E256 Data Sheet, Rev. 1.08
Chapter 4, “Clocks and Reset Generator
and
Chapter 14, “Dual Output
(CRGV4)”.
Freescale Semiconductor
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