mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 441

• Manufacturer Part Number: mc9s12e256
• Description: Hcs12 Microcontrollers 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

14.3.2
The following paragraphs describe, in address order, all the VREG registers and their individual bits.
14.3.2.1
The VREGCTRL register allows to separately enable features of VREG.
14.4
Block VREG is a voltage regulator as depicted in
regulator core (REG), a low-voltage detect module (LVD), a power-on reset module (POR) and a
low-voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the
interface to the digital core logic but also manages the operating modes of VREG.
14.4.1
VREG, respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2)
that differ only in the amount of current that can be sourced to the connected loads. Therefore, only REG1
providing the supply at V
Freescale Semiconductor
Reset
LVDS
Field
LVIE
LVIF
2
1
0
W
R
Functional Description
Register Descriptions
REG — Regulator Core
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
VREG — Control Register (VREGCTRL)
0
0
7
On entering the reduced-power mode the LVIF is not cleared by the VREG.
= Unimplemented or Reserved
Figure 14-2. VREG3V3 — Control Register (VREGCTRL)
DD
0
0
6
DDA
DDA
/V
SS
is above level V
is below level V
Table 14-3. VREGCTRL Field Descriptions
is explained. The principle is also valid for REG2.
MC9S12E256 Data Sheet, Rev. 1.08
0
0
5
LVIA
LVID
and FPM.
or RPM or shutdown mode.
NOTE
Figure
0
0
4
Description
14-1. The regulator functional elements are the
Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
3
0
0
LVDS
0
2
LVIE
0
1
LVIF
0
0
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