mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 138

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mc9s12ne64

Manufacturer Part Number
mc9s12ne64
Description
Hcs12 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 3 Port Integration Module (PIM9NE64V1)
If IIC takes precedence thePJ[7:6] pins become IIC open drain output pins.
During reset, pins PJ[7:6] are configured as inputs with pull-ups and pins PJ[3:0] are configured as
high-impedance inputs.
3.4.11
In all modes, port L pins PL[6:0] can be used either for general-purpose I/O or with the EPHY subsystem.
During reset, port L pins are configured as inputs with pull-ups.
3.4.12
All port and pin logic is located in the core module. Please refer to MEBI block description chapter for
details.
3.4.13
All ports start up as general-purpose inputs on reset.
3.4.14
3.4.14.1 Run Mode
No low power options exist for this module in run mode.
3.4.14.2 Wait Mode
No low power options exist for this module in wait mode.
3.4.14.3 Stop Mode
All clocks are stopped. There are asynchronous paths to generate interrupts from STOP on port G, H, and J.
3.5
The reset values of all registers are given in
3.5.1
All registers including the data registers get set/reset asynchronously.
properties after reset initialization.
138
Initialization/Application Information
Port L
Port A, B, E and BKGD Pin
External Pin Descriptions
Low Power Options
Reset Initialization
MC9S12NE64 Data Sheet, Rev. 1.1
Section 3.3, “Memory Map and Register
Table 3-5
summarizes the port
Freescale Semiconductor
Descriptions.”

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